Scalable VLSI architecture for variable block size integer motion estimation in H.264/AVC

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E89-A, Issue 4, 2006, Pages 979-987

  Song, Yang ^a   Liu, Zhenyu ^b,c   Goto, Satoshi ^a,d,e   Ikenaga, Takeshi ^a,d,f  

^a WASEDA UNIVERSITY   (Japan)

^b Kitakyushu Foundation for the Advancement of Industry Science and Technolstockholmogy   (Japan)

^c Kitakyushu Foundation for the Advancement of Industry Science and Technology   (Japan)

^d IEEE

^e Academy Engineering Society of Japan   (Japan)

^f IPSJ   (Japan)

Author keywords

H.264 AVC; Variable block size motion estimation (VBSME); Very large scale integration (VLSI) architecture

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; MOTION ESTIMATION; PARALLEL PROCESSING SYSTEMS; STATIC RANDOM ACCESS STORAGE;

H.264/AVC; VARIABLE BLOCK SIZE MOTION ESTIMATION (VBSME); VERY LARGE SCALE INTEGRATION (VLSI) ARCHITECTURE;

VLSI CIRCUITS;

EID: 33646244730     PISSN: 09168508     EISSN: 17451337     Source Type: Journal    
DOI: 10.1093/ietfec/e89-a.4.979     Document Type: Conference Paper

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