Low cost efficient architecture for H.264 motion estimation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 412-415

  López, Sebastián ^a   Tobajas, Félix ^a   Villar, Arturo ^a   De Armas, Valentín ^a   López, José Fco ^a   Sarmiento, Roberto ^a  

^a UNIVERSITY OF LAS PALMAS DE GRAN CANARIA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

H.264/AVC VIDEO CODING STANDARD; LOW COSTS; MOTION VECTORS; MULTIMEDIA DEVICE; OPERATION FREQUENCY; PARTIAL DISTORTION ELIMINATION; POWER DISSIPATION; PROPOSED ARCHITECTURES; VLSI ARCHITECTURES;

IMAGE CODING; MOTION PICTURE EXPERTS GROUP STANDARDS; VISUAL COMMUNICATION;

MOTION ESTIMATION;

EID: 34547601014     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464612     Document Type: Conference Paper

References (9)

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7. P. Kuhn, U. Niedermeier, L.-F. Chao, W. Stechele, "A flexible low power VLSI architecture for MPEG-4 motion estimation," Proc. of SPIE Conference on Visual Communications and Image Processing '99, vol. 3653, pp. 883-894, Jan. 1999
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