A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1, Issue , 2005, Pages 631-634

  Kim, Minho ^a   Hwang, Ingu ^a   Chae, Soo Ik ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; MOTION PICTURE EXPERTS GROUP STANDARDS; VLSI CIRCUITS;

DATA BUFFERS; DIFFERENT SIZES; MOTION VECTORS; REALTIME PROCESSING; SEARCH AREA; SEARCH RANGE; VARIABLE BLOCK-SIZE MOTION ESTIMATION; VLSI ARCHITECTURES;

MOTION ESTIMATION;

EID: 84861444464     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120980     Document Type: Conference Paper

References (5)

1. Swee Yeow Yap, John V. McCanny, "A VLSI architecture for advanced video coding motion estimation," Proc. IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP'03), June 24-26, 2003.
2. Cao Wei, Mao Zhi Gang, "A novel SAD computing hardware architecture for variable-size block motion estimation and its implementation with FPGA," Proc. 5th international conference on ASIC, Oct 21-24, 2003.
3. P. M. Kuhn, A. Weisgerber, R. Poppenwimmer, and W. Stechele, "A flexible VLSI architecture for variable block size segment matching with luminance correction," IEEE International conference on Application-specific Systems, Architectures, and Processors (ASAP 97), Zurich, 1997.
4. Yu-Wen Huang, Tu-Chih Wang, Bing-Yu Hsieh, and Liang-Gee Chen, "Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264," Proc. IEEE International Symposium on Circuits and Systems(ISCAS 2003), Bangkok, Thailand, May 2003.
5. Jen-Chieh Tuan, Tian-Sheuan Chang, "On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture," IEEE Transactions on circuits and systems for video technology, vol.12, no. 1, Jan. 2002.