Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 16, Issue 6, 2006, Pages 673-688

  Chen, Tung Chien ^b   Chien, Shao Yi ^b   Huang, Yu Wen ^b   Tsai, Chen Han ^b   Chen, Ching Yeh ^b   Chen, To Wei ^b   Chen, Liang Gee ^a,b  

^a IEEE   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

ISO IEC 14496 10 AVC; ITU T Rec. H.264; Joint Video Team (JVT); Single chip video encoder; Very large scale integration (VLSI) architecture

Indexed keywords

ISO/IEC 14496-10 AVC; ITU-T REC. H.264; JOINT VIDEO TEAM (JVT); SINGLE-CHIP VIDEO ENCODER; VERY LARGE-SCALE INTEGRATION (VLSI) ARCHITECTURE;

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; LOGIC GATES; MOTION ESTIMATION; PARALLEL PROCESSING SYSTEMS; REAL TIME SYSTEMS; STATIC RANDOM ACCESS STORAGE;

IMAGE CODING;

EID: 33746358201     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSVT.2006.873163     Document Type: Article

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