A VLSI Architecture for Variable Block Size Video Motion Estimation

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 51, Issue 7, 2004, Pages 384-389

  Yap, Swee Yeow ^a   McCanny, John V ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

Advanced video coding (AVC); sum of absolute difference (SAD); variable block size motion estimation (VBSME); very large scale integration (VLSI) architecture

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; FLIP FLOP CIRCUITS; IMAGE CODING; IMAGE SEGMENTATION; MOTION ESTIMATION; MULTIPLEXING EQUIPMENT; SEMICONDUCTING SILICON; TABLE LOOKUP; TELEVISION STANDARDS;

ADVANCED VIDEO CODING; CURRENT MACROBLOCK DATA; MOTION VECTOR; SEARCH REGION DATA; VARIABLE BLOCK SIZE MOTION ESTIMATION;

VLSI CIRCUITS;

EID: 3543021496     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2004.829555     Document Type: Article

References (8)

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