Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2007, Pages 160-163

  Liu, Zhenyu ^a   Huang, Yiqing ^a   Song, Yang ^a   Goto, Satoshi ^a   Ikenaga, Takeshi ^a  

^a WASEDA UNIVERSITY   (Japan)

Author keywords

H.264; Variable block size motion estimation; VLSI

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; IMAGE COMPRESSION; MOTION ESTIMATION; REAL TIME SYSTEMS; VIDEO SIGNAL PROCESSING; VLSI CIRCUITS;

DATAPATH LOGIC; REAL TIME ENCODING; VARIABLE BLOCK SIZE MOTION ESTIMATION;

IMAGE CODING;

EID: 34748923444     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1228784.1228826     Document Type: Conference Paper

References (8)

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