Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2003, Pages

  Huang, Yu Wen ^a   Wang, Tu Chih ^a   Hsieh, Bing Yu ^a   Chen, Liang Gee ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BROADCASTING; COMPUTER HARDWARE; COMPUTER SIMULATION; PARALLEL PROCESSING SYSTEMS;

VARIABLE BLOCK SIZE;

MOTION ESTIMATION;

EID: 0038421877     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Committee Draft of Joint Video Specification (ITU-T Rec. H.264 and ISO/IEC 14496-10 AVC), July, 2002.
2. Joint Video Team (JVT) software JM4.0d, August, 2002.
3. T.C. Wang, Y.W. Huang, H.C. Fang, and L.G. Chen, "Performance analysis of hardware oriented algorithm modifications in H.264," submitted to IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003.