High rate wave-pipelined asynchronous on-chip bit-serial data link

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2007, Pages 3-14

  Dobkin, Rostislav Reuven ^a   Perelman, Yevgeny ^a   Liran, Tuvia ^a   Ginosar, Ran ^a   Kolodny, Avinoam ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

SIGNAL ENCODING;

BIT-SERIAL; CYCLE TIME; DATA BITS; HIGH DATA RATE; HIGH DATA-RATES; HIGH RATE; ON CHIP COMMUNICATION; ON CHIPS; SERIAL DATA LINK; SERIAL LINK;

SHIFT REGISTERS;

EID: 51749120681     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/async.2007.20     Document Type: Conference Paper

References (29)

1. International Technology Roadmap for Semiconductors (ITRS), 2005, www.itrs.net.
2. R. Ho, K.W. Mai, M.A. Horowitz, "The Future of Wires," Proc. of the IEEE, 89(4), pp. 490-504, 2001.
3. A. Morgenshtein, I. Cidon, A. Kolodny, R. Ginosar, "Low-Leakage Repeaters for NoC Interconnects", Special Session "Repeater Insertion for Nanometer Technologies-Timing is NOT Everything", Proc. of ISCAS, pp. 600-603, 2005.
4. R. Weerasekera, D. Pamunuwa, L. Zheng and H. Tenhunen, "Minimal-Power, Delay-Balanced Smart Repeaters for Interconnects in the Nanometer Regime," Proc. of SLIP, pp. 113-120, 2006.
5. K. Lee, S.J. Lee, H.J. Yoo, "SILENT: serialized low energy transmission coding for on-chip interconnection networks," Proc. of ICCAD-2004, pp. 448-451, 2004.
6. R. Dobkin, A. Morgenshtein, A. Kolodny, R. Ginosar, "Long Range On-Chip Communication: Parallel or Serial?" CCIT TR, Electrical Engineering Dept., Technion-Israel Institute of Technology, 2006.
7. J. Teifel, R. Manohar, "A High-Speed Clockless Serial Link Transceiver," Proc. ASYNC'03, pp. 151-161, 2003.
8. R. Dobkin, R. Ginosar, A. Kolodny, "Fast Asynchronous Shift Register for Bit-Serial Communication," Proc. of ASYNC'06, 2006.
9. R.H. Mak, "Design and performance analysis of buffers: a constructive approach," Proc. of ASYNC, pp. 137-148, 2002.
10. C.H. Kees van Berkel, M. Rem, R. Saeijs, VLSI programming, in: IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1998, pp. 152-156.
11. R. Dobkin, R. Ginosar, A. Kolodny, "High-Speed Serial Interconnect for NoC," NoC Workshop, DATE'06, 2006.
12. A.P. Jose, G. Patounakis, K.L. Shepard, "Pulsed Current-Mode Signaling for Nearly Speed-of-Light Intrachip Communication," Journal of Solid-State Circuits, 41(4), pp. 772-780, 2006.
13. I. Saastamoinen, T. Suutari, J. Isoaho and J. Nurmi, "Interconnect IP for Gigascale System-on-chip," Proc. of Euro. Conf. Circuit Theory and Design (ECCTD), pp. 281-284, 2001.
14. T. Suutari, J. Isoaho and H. Tenhunen, "High-speed Serial Communication with Error Correction Using 0.25?m CMOS Technology," Proc. ISCAS, pp. IV-618-621, 2001.
15. S.J. Lee, K. Kim, H. Kim, N. Cho, H.J. Yoo, "Adaptive Network-on-Chip with Wave-front Train Serialization Scheme," Proc. of VLSI Circuits, pp. 104-107, 2005.
16. G. Lakshminarayanan, B. Venkataramani, "Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks," IEEE Trans. VLSI, 13(7), pp. 783-793, 2005.
17. C. Svensson and J. Yuan, "A 3-Level Asynchronous protocol for a Differential Two-Wire Communication Link," J. Solid State Circuits, 29(9), pp. 1129-1132, 1994.
18. M.J.E. Lee, "An Efficient I/O and Clock Recovery for TERABIT Integrated Circuits Design," PhD Thesis, Stanford Univ., 2001.
19. C.K.K. Yang, "Design of High-Speed Serial Links in CMOS", PhD Thesis, Stanford University, 1998.
20. R. Dobkin, R. Ginosar and C. P. Sotiriou, "High Rate Data Synchronization in GALS SoCs," IEEE Transactions on VLSI, 14(10), pp. 1063-1074, 2006.
21. M.T. Dean, T. Williams et al. "Efficient Self-Timing with Level-Encoded 2-Phase Dual-Rail (LEDR)," Proc. ARVLSI, pp. 55-70, 1991.
22. D.H. Linder and J.C. Harden, "Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry," IEEE Trans. Computers 45(9), pp. 1031-1044, 1996.
23. I.E. Sutherland, "Inverse XOR and XNOR Circuits," US Patent 5,861,762, 1999.
24. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev, "Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers," IEICE Transactions on Information and Systems, E80-D(3), pp. 315-325, 1997.
25. H.Kaul, D.Sylvester and D.Blaauw, "Active Shields: A New Approach to Shielding Global Wires," Proc. Great Lakes Symposium on VLSI, pp. 112-117, April, 2002.
26. H. Johnson, M. Graham, "High-Speed Digital Design. A handbook of Black Magic", Prentice Hall PTR, 1993.
27. C. Svensson, P Caputa, "High bandwidth, low latency global interconnect", Proc. of SPIE conference, Canary Islands, pp. 126-134, 2003.
28. Berkeley Predictive Technology Model (BPTM), http://www.eas.asu.edu/~ptm.
29. Synopsys, Inc., Raphael. http://www.synopsys.com.