High bandwidth, low latency global interconnect

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5117, Issue , 2003, Pages 126-134

  Svensson, Christer ^a   Caputa, Peter ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

Global; High bandwidth; Interconnect; Low latency

Indexed keywords

BANDWIDTH; CHANNEL CAPACITY; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT MANUFACTURE; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

GLOBAL INTERCONNECT; SOFTWARE PACKAGE HSPICE; SYSTEM ON CHIP;

INTEGRATED CIRCUIT LAYOUT;

EID: 0042329208     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.499957     Document Type: Conference Paper

References (18)

1. C. Mead and L. Conway, Introduction to VLSI Systems, Addison-Wesley, 1980.
2. H. Bakoglu, Circuits, Interconnection and Packaging for VLSI, Addison-Wesley, 1990.
3. C. Svensson and M. Afghahi, "On RC Line Delays and Scaling in VLSI Systems", Electronic Lett., 24, 562-563, 1988.
4. W.J. Dally and J. W. Poulton, Digital Systems Engineering, Cambridge University Press, 1998.
5. A. Deutsch, et. al., "On-Chip Wiring Design Challenges for Gigahertz Operation", Proc. IEEE, 89, 529-555, 2001.
6. C. Svensson, "Electrical Interconnects Revitalized", IEEE Trans. of VLSI Systems, 10, 777-788, 2002.
7. L. Benini and G. De Micheli, "Network on Chips: A New Soc Paradigm", IEEE Computer, 35, 70-80, 2002.
8. K. Gocssens, J. Dielissen, J. van Meerbergen, P. Poplavko, A. Radulescu, E. Rijpkema, E. Waterlander, and P. Wielage, "Guaranteeing the quality of services in networks on chip", Networks on Chip, Axel Jantsch and Hannu Tenhunen, Kluwer, 2002.
9. Dake Liu, Daniel Wiklund, Eric Svensson, Olle Seger, and Sumant Sathe, "SoCBUS: The solution of high communication bandwidth on chip and short TTM" Proc of the Real-Time and Embedded Computing Conference, Gothenburg, Sweden, 2002.
10. Daniel Wiklund and Dake Liu "SoCBUS: Switched Network on Chip for Hard Real Time Systems" to appear at the IPDPS'03, Nice, France, 2003
11. C. Svensson and G. Dermer, "Time Domain Modeling of Lossy Interconnects", IEEE Transactions on Advanced Packaging, 24, 19, 2001.
12. J. M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits, Second edition, Prentice Hall, 2003.
13. A. Fiedler, R. Mactaggart, J. Welch and S. Krishnan, "A 1.0625Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-emphasis", 1997 Int. Solid State Circuit Conference, Digest of Technical Papers, 238-239, 1997.
14. Oh-Kyong Kwon, R. Fabian W. Pease, "Closely Packed Microstrip Lines as Very High-Speed Chip-to-Chip Interconnects", IEEE Transactions on Components, Hybrids, and Manufacturing Technology, CHMT-10, 1987.
15. C. Svensson, "Optimum Voltage Swing on On-Chip and Off-Chip Interconnects", IEEE J. Solid-State Circuits, 36, 1108-1112, 2001.
16. P. Caputa and C. Svensson, "Low-Power, Low-Latency Global Interconnect", 15th Annual IEEE International ASIC/SOC Conference, Rochester, Sept. 25-28, 2002.
17. B. J. Benschneider et. al., "A 1GHz Alpha Microprocessor", 2000 IEEE Solid-State Circuits Conference, Digest of Technical Papers, 86-87, 2000.
18. F. Mu and C. Svensson, "Self-tested Self-Synchronization Circuit for Mesochronous Clocking", IEEE Trans. on Circuits and Systems - II, 48, 129-140, 2001.