Modeling and estimation of full-chip leakage current considering within-die correlation

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 93-98

  Heloue, Khaled R ^a   Azizi, Navid ^a   Najm, Farid N ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

Leakage power; Statistical analysis

Indexed keywords

CHIP SCALE PACKAGES; COMPUTER SIMULATION; ERROR ANALYSIS; LOGIC DEVICES; STATISTICAL METHODS;

DIE CORRELATION; FULL-CHIP LEAKAGE; GATE COUNT; SPATIAL CORRELATION;

LEAKAGE CURRENTS;

EID: 34547369754     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375131     Document Type: Conference Paper

References (8)

1. S. Narendra, V. De, D. Antoniadis, and A. Chandrakasan. Pull-chip sub-threshold leakage power prediction model of sub-0.18μm CMOS. ISLPED, 2002.
2. R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester. Statistical analysis of subthreshold leakage current for VLSI circuits. TVLSI, 12(2):131-139, February 2004.
3. H. Chang and S. S. Sapatnekar. Full-chip analysis of leakage power under process variations, including spatial correlations. DAC, 2005.
4. A. Agarwal, K. Kang, and K. Roy. Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations. ICCAD, 2005.
5. J. Xiong, V. Zolotov, and L. He. Robust extraction of spatial correlation. ISPD, 2006.
6. A. Keshavarzi, et al. Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage. ISLPED, 2005.
7. A. Papoulis. Probability, Random Variables, and Stochastic Processes. McGraw-Hill, New York, NY, 2nd edition, 1984.
8. D. Helms, et al. Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation. ISLPED, 2006.