메뉴 건너뛰기




Volumn , Issue , 2006, Pages 103-108

Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions

Author keywords

Leakage power; Statistical analysis

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; ERROR CORRECTION; MICROPROCESSOR CHIPS; MONTE CARLO METHODS; STATISTICAL METHODS;

EID: 34547156269     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1146941     Document Type: Conference Paper
Times cited : (40)

References (16)
  • 1
    • 85165852190 scopus 로고    scopus 로고
    • Semiconductor Industry Associate, International Technology Roadmap for Semiconductors, 2004.
    • Semiconductor Industry Associate, International Technology Roadmap for Semiconductors, 2004.
  • 2
    • 0042697357 scopus 로고    scopus 로고
    • Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
    • Feb
    • K. Roy, S. Mukhopadhyay and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
    • (2003) Proc. IEEE , vol.91 , Issue.2 , pp. 305-327
    • Roy, K.1    Mukhopadhyay, S.2    Mahmoodi-Meimand, H.3
  • 4
    • 0036949325 scopus 로고    scopus 로고
    • Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
    • S. Narendra, V. De, S. Borkar, D. Antoniadis and A. Chandrakasan, "Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS," IEEE ISLPED, pp. 19-23, 2002.
    • (2002) IEEE ISLPED , pp. 19-23
    • Narendra, S.1    De, V.2    Borkar, S.3    Antoniadis, D.4    Chandrakasan, A.5
  • 5
    • 85084686867 scopus 로고    scopus 로고
    • Statistical estimation of leakage current considering inter- and intra-die process variation
    • R. Rao, A. Srivastava, D. Blaauw and D. Sylvester, "Statistical estimation of leakage current considering inter- and intra-die process variation," IEEE ISLPED, pp. 84-89, 2003.
    • (2003) IEEE ISLPED , pp. 84-89
    • Rao, R.1    Srivastava, A.2    Blaauw, D.3    Sylvester, D.4
  • 6
    • 4444351567 scopus 로고    scopus 로고
    • Parametric yield estimation considering leakage variability
    • R. Rao, A. Devgan, D. Blaauw and D. Sylvester, "Parametric yield estimation considering leakage variability," IEEE DAC, pp. 442-447, 2004.
    • (2004) IEEE DAC , pp. 442-447
    • Rao, R.1    Devgan, A.2    Blaauw, D.3    Sylvester, D.4
  • 7
    • 27944464454 scopus 로고    scopus 로고
    • Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance
    • A. Srivastava, S. Shah, K. Agarwal, D. Sylvester, D. Blaauw and S. Director, "Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance," IEEE DAC, pp. 535-540, 2005.
    • (2005) IEEE DAC , pp. 535-540
    • Srivastava, A.1    Shah, S.2    Agarwal, K.3    Sylvester, D.4    Blaauw, D.5    Director, S.6
  • 8
    • 0042090415 scopus 로고    scopus 로고
    • Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling
    • S. Mukhopadhyay, A. Raychowdhury and K. Roy, "Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling," IEEE DAC, pp. 169-174, 2003.
    • (2003) IEEE DAC , pp. 169-174
    • Mukhopadhyay, S.1    Raychowdhury, A.2    Roy, K.3
  • 9
    • 15244338765 scopus 로고    scopus 로고
    • Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile
    • Mar
    • S. Mukhopadhyay, A. Raychowdhury and K. Roy, "Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile," IEEE Trans. CAD, vol. 24, no. 3, pp. 363-381, Mar. 2005.
    • (2005) IEEE Trans. CAD , vol.24 , Issue.3 , pp. 363-381
    • Mukhopadhyay, S.1    Raychowdhury, A.2    Roy, K.3
  • 10
    • 27944470947 scopus 로고    scopus 로고
    • Full-chip analysis of leakage power under process variations, including spatial correlations
    • H. Chang, S. Sapatnekar, "Full-chip analysis of leakage power under process variations, including spatial correlations," IEEE DAC, pp. 523-528, 2005.
    • (2005) IEEE DAC , pp. 523-528
    • Chang, H.1    Sapatnekar, S.2
  • 11
    • 33751551819 scopus 로고    scopus 로고
    • Projection-based performance modeling for inter/intra-die variations
    • X. Li, J. Le, L. Pileggi and A. Strojwas, "Projection-based performance modeling for inter/intra-die variations," IEEE ICCAD, pp. 721-727, 2005.
    • (2005) IEEE ICCAD , pp. 721-727
    • Li, X.1    Le, J.2    Pileggi, L.3    Strojwas, A.4
  • 12
    • 16244393708 scopus 로고    scopus 로고
    • Asymptotic probability extraction for non-Normal distributions of circuit performance
    • X Li, J. Le, P. Gopalakrishnan and L. Pileggi, "Asymptotic probability extraction for non-Normal distributions of circuit performance," IEEE ICCAD, pp. 2-9, 2004.
    • (2004) IEEE ICCAD , pp. 2-9
    • Li, X.1    Le, J.2    Gopalakrishnan, P.3    Pileggi, L.4
  • 16
    • 0032139262 scopus 로고    scopus 로고
    • PRIMA: Passive reduced-order interconnect macromodeling algorithm
    • Aug
    • A. Odabasioglu, M. Celik and L. Pileggi, "PRIMA: passive reduced-order interconnect macromodeling algorithm," IEEE Trans. CAD, vol. 17, no. 8, pp. 645-654, Aug. 1998.
    • (1998) IEEE Trans. CAD , vol.17 , Issue.8 , pp. 645-654
    • Odabasioglu, A.1    Celik, M.2    Pileggi, L.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.