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1
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85165852190
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Semiconductor Industry Associate, International Technology Roadmap for Semiconductors, 2004.
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Semiconductor Industry Associate, International Technology Roadmap for Semiconductors, 2004.
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2
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0042697357
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Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
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Feb
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K. Roy, S. Mukhopadhyay and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
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Roy, K.1
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3
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0041633858
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Parameter variations and impact on circuits and microarchitecture
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S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi and V. De, Parameter variations and impact on circuits and microarchitecture," IEEE DAC, pp. 338-342, 2003.
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Borkar, S.1
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Narendra, S.3
Tschanz, J.4
Keshavarzi, A.5
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4
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0036949325
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Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
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S. Narendra, V. De, S. Borkar, D. Antoniadis and A. Chandrakasan, "Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS," IEEE ISLPED, pp. 19-23, 2002.
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Chandrakasan, A.5
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5
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85084686867
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Statistical estimation of leakage current considering inter- and intra-die process variation
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R. Rao, A. Srivastava, D. Blaauw and D. Sylvester, "Statistical estimation of leakage current considering inter- and intra-die process variation," IEEE ISLPED, pp. 84-89, 2003.
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Rao, R.1
Srivastava, A.2
Blaauw, D.3
Sylvester, D.4
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6
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4444351567
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Parametric yield estimation considering leakage variability
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R. Rao, A. Devgan, D. Blaauw and D. Sylvester, "Parametric yield estimation considering leakage variability," IEEE DAC, pp. 442-447, 2004.
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IEEE DAC
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Rao, R.1
Devgan, A.2
Blaauw, D.3
Sylvester, D.4
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7
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Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance
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A. Srivastava, S. Shah, K. Agarwal, D. Sylvester, D. Blaauw and S. Director, "Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance," IEEE DAC, pp. 535-540, 2005.
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Agarwal, K.3
Sylvester, D.4
Blaauw, D.5
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8
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0042090415
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Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling
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S. Mukhopadhyay, A. Raychowdhury and K. Roy, "Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling," IEEE DAC, pp. 169-174, 2003.
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Mukhopadhyay, S.1
Raychowdhury, A.2
Roy, K.3
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9
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15244338765
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Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile
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Mar
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S. Mukhopadhyay, A. Raychowdhury and K. Roy, "Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile," IEEE Trans. CAD, vol. 24, no. 3, pp. 363-381, Mar. 2005.
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Mukhopadhyay, S.1
Raychowdhury, A.2
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10
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27944470947
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Full-chip analysis of leakage power under process variations, including spatial correlations
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H. Chang, S. Sapatnekar, "Full-chip analysis of leakage power under process variations, including spatial correlations," IEEE DAC, pp. 523-528, 2005.
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IEEE DAC
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Chang, H.1
Sapatnekar, S.2
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11
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33751551819
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Projection-based performance modeling for inter/intra-die variations
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X. Li, J. Le, L. Pileggi and A. Strojwas, "Projection-based performance modeling for inter/intra-die variations," IEEE ICCAD, pp. 721-727, 2005.
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12
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Asymptotic probability extraction for non-Normal distributions of circuit performance
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X Li, J. Le, P. Gopalakrishnan and L. Pileggi, "Asymptotic probability extraction for non-Normal distributions of circuit performance," IEEE ICCAD, pp. 2-9, 2004.
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Li, X.1
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Gopalakrishnan, P.3
Pileggi, L.4
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16
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0032139262
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PRIMA: Passive reduced-order interconnect macromodeling algorithm
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Aug
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A. Odabasioglu, M. Celik and L. Pileggi, "PRIMA: passive reduced-order interconnect macromodeling algorithm," IEEE Trans. CAD, vol. 17, no. 8, pp. 645-654, Aug. 1998.
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