Timing yield estimation using statistical static timing analysis

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 2461-2464

  Pan, Min ^a   Chu, Chris Chong Nuen ^a   Zhou, Hai ^b  

^a IOWA STATE UNIVERSITY   (United States)

^b NORTHWESTERN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE ERRORS; CIRCUIT TIMING; CLOCK SKEWS; DEEP SUB-MICRON TECHNOLOGY; DELAY DISTRIBUTIONS; DESIGN METHOD; HIGH-PERFORMANCE CIRCUITS; HOLD TIME; MONTE CARLO SIMULATION; PATH DELAY; PROCESS VARIATION; RECONVERGENCE; SET-UP TIME; SHORTEST PATH; STATIC TIMING ANALYSIS; STATISTICAL APPROACH; STATISTICAL STATIC TIMING ANALYSIS; TIMING YIELD;

ELECTRIC CLOCKS; INTEGRATED CIRCUIT MANUFACTURE; MONTE CARLO METHODS; SYSTEMS ANALYSIS; TIME MEASUREMENT; TIMING DEVICES;

TIMING CIRCUITS;

EID: 51549108005     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465124     Document Type: Conference Paper

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