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Volumn , Issue , 2001, Pages 122-124

Technology scaling impact of variation on clock skew and interconnect delay

Author keywords

[No Author keywords available]

Indexed keywords


EID: 85001134901     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2001.930035     Document Type: Conference Paper
Times cited : (49)

References (11)
  • 1
    • 0001240604 scopus 로고    scopus 로고
    • A Mathematical Model of Pattern Dependencies in Cu CMP Processes
    • Oct.
    • T. Tugbawa et al., "A Mathematical Model of Pattern Dependencies in Cu CMP Processes," Proc. CMP Symposium, Electrochemical Society, Oct. 1999.
    • (1999) Proc. CMP Symposium, Electrochemical Society
    • Tugbawa, T.1
  • 2
    • 85036636304 scopus 로고    scopus 로고
    • Optimum Chip Clock Distribution Networks
    • June
    • P. Zarkesh-Ha et al., "Optimum Chip Clock Distribution Networks," Proc. IITC, June 1999.
    • (1999) Proc. IITC
    • Zarkesh-Ha, P.1
  • 3
    • 84950107446 scopus 로고    scopus 로고
    • Design for Variability in DSM Technologies
    • S. Nassif, "Design for Variability in DSM Technologies," Proc. ISQED, 2000.
    • (2000) Proc. ISQED
    • Nassif, S.1
  • 4
    • 85001141338 scopus 로고    scopus 로고
    • Modeling the Effects of Manufacturing Variation on High-Speed Microprocessor Interconnect Performance
    • Dec.
    • V. Mehrotra et al., "Modeling the Effects of Manufacturing Variation on High-Speed Microprocessor Interconnect Performance" Proc. IEDM, Dec. 1998.
    • (1998) Proc. IEDM
    • Mehrotra, V.1
  • 5
    • 0033719785 scopus 로고    scopus 로고
    • A Methodology for Modeling the Effects of Systematic Within-Die Interconnect and Device Variation on Circuit Performance
    • June
    • V. Mehrotra et al., "A Methodology for Modeling the Effects of Systematic Within-Die Interconnect and Device Variation on Circuit Performance," Proc. DAC, June 2000.
    • (2000) Proc. DAC
    • Mehrotra, V.1
  • 6
    • 0031382548 scopus 로고    scopus 로고
    • Understanding Across Chip Linewidth Variation: The First Step Toward Optical Proximity Collection
    • L. Liebmann et al., "Understanding Across Chip Linewidth Variation: The First Step Toward Optical Proximity Collection," Proc. SPIE, vol. 3051, 1997.
    • (1997) Proc. SPIE , vol.3051
    • Liebmann, L.1
  • 7
    • 0032205065 scopus 로고    scopus 로고
    • Simulating the Impact of Poly-CD Variation on Circuit Performance
    • Nov.
    • B. Stine et al., "Simulating the Impact of Poly-CD Variation on Circuit Performance," IEEE Trans. Semiconductor Manufacturing, vol. 11, no. 4, Nov. 1998.
    • (1998) IEEE Trans. Semiconductor Manufacturing , vol.11 , Issue.4
    • Stine, B.1
  • 8
    • 0020704286 scopus 로고
    • Simple Formul as for Two- and Three- Dimensional Capacitances
    • T. Sakurai, "Simple Formul as for Two- and Three- Dimensional Capacitances," IEEE Trans. Electron Devices, vol. ED-30, no.2, 1983.
    • (1983) IEEE Trans. Electron Devices , vol.ED-30 , Issue.2
    • Sakurai, T.1
  • 10
    • 85001138152 scopus 로고    scopus 로고
    • A 1GHz Single-Issue 64b PowerPC Processor
    • Feb.
    • H. Hofstee et al., "A 1GHz Single-Issue 64b PowerPC Processor, "Proc. ISSCC, Feb. 2000.
    • (2000) Proc. ISSCC
    • Hofstee, H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.