A "True" electrical cell model for timing, noise, and power grid verification

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 462-467

  Menezes, Noel ^a   Kashyap, Chandramouli ^a   Amin, Chirayu ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Cell models; Current source models; Static timing analysis

Indexed keywords

CELL MODELING; CELL MODELS; CURRENT SOURCE MODELS; STATIC TIMING ANALYSIS;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; INDUSTRIAL ENGINEERING; LIMITERS; POWER GENERATION; STATIC ANALYSIS; TIME MEASUREMENT;

CELLS;

EID: 51549101678     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555862     Document Type: Conference Paper

References (23)

1. C. Visweswariah, "Death, taxes, and failing chips," Proc. of DAC, pp. 343-347, 2003.
2. D. Blaauw, S. Sirichotiyakul, and C. Oh, "Driver modeling and alignment for worst-case delay noise," IEEE Trans. on VLSI, pp. 157-165, Apr. 2003.
3. D. Kouroussis, R. Ahmadi, F. Najm, "Worst-case delay taking into account power supply variations," Proc. of DAC, pp. 652-657, 2004.
4. F. Dartu, N. Menezes, and L. T. Pileggi, "Performance computation for precharacterized CMOS gates with RC loads," IEEE Trans. on CAD, vol. 15, no. 5, pp. 544-553, May 1996.
5. J. F. Croix and D. F. Wong, "Blade and Razor: Cell and interconnect delay analysis using current-based models," Proc. of DAC, pp. 386-389, 2003.
6. I. Keller, K. Tseng, and N. Verghese, "A robust cell-level crosstalk delay change analysis," Proc. of ICCAD, pp. 147-154, Nov. 2004.
7. P. Li and E. Acar, "Waveform independent gate models for accurate timing analysis", Proc. of ICCD, pp. 363-365, Oct. 2005.
8. C. Amin, C. Kashyap, N. Menezes, K. Killpack and E. Chiprout, "A multi-port current source model for multipleinput switching effects in CMOS library cells," Proc. of DAC, pp. 247-252, Jul. 2006.
9. V. Veetil, D. Sylvester, and D. Blaauw, "Fast and accurate waveform analysis with current source models," TAU workshop presentation, Feb. 2007.
10. H. Fatemi, S. Nazarian, and M. Pedram, "A current-based method for short circuit power calculation under noisy input waveforms," Proc. of ASP-DAC, pp. 774-779, 2007.
11. C. Kashyap, C. Amin, N. Menezes, and E. Chiprout, "A nonlinear cell macromodel for digital applications," Proc. of ICCAD, 2007.
12. F. Dartu and L. T. Pileggi, "Calculating worst-case gate delays due to dominant capacitance coupling," Proc. of DAC, pp. 46-51, Jun. 1997.
13. C. Amin, F. Dartu, and Y. I. Ismail, "Weibull based analytical waveform model," Proc. of ICCAD, pp. 161-168, Nov. 2005.
14. S. R. Nassif and E. Acar, "Advanced waveform models for the nanometer regime," TAU workshop presentation, 2004.
15. V. Chandramouli and K. A. Sakallah, "Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time," Proc. of DAC, pp. 617-622, Jun. 1996.
16. L-C Chen, S. K. Gupta, M. A. Breuer, "A new gate delay model for simultaneous switching and its applications," Proc. of DAC, pp. 289-294, Jun. 2001.
17. F. Dartu, K. Killpack, C. Amin, and N. Menezes, "Evaluating the factors influencing timing accuracy," TAU workshop presentation, Feb. 2005.
18. J. Qian, S. Pullela, and L. Pillage, "Modeling the effective capacitance for the RC interconnect of CMOS gates," IEEE Trans. on CAD, vol. 13, no. 12, pp. 1526-1535, Dec. 1994.
19. "CCS timing white paper," Composite Current Source, Synopsys, [online], http://www.synopsys.com/products/soluti on s/galaxy/ccs/cc_source. html, 2005.
20. "Delay calculation meets the nanometer era," Cadence Technical Paper, [online] http://www.cadence.com/products/digital_ic/tech_info.aspx, 2005.
21. B. Tutuianu, R. Baldick, and M. S. Johnstone, "Nonlinear driver models for timing and noise analysis," IEEE Trans. on CAD, vol. 23, no. 11, pp. 1510-1521, Nov. 2004.
22. M. Rewienski and J. White, "A trajectory piece-wise linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices," IEEE Trans. on CAD, vol. 22, no. 2, pp. 155-170, 2003.
23. N. Dong and J. Roychowdhury, "Automated nonlinear macromodeling of output buffers for high speed digital applications," Proc. of DAC, pp. 51-56, 2005.