A nonlinear cell macromodel for digital applications

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 678-685

  Kashyap, Chandramouli ^a   Amin, Chirayu ^a   Menezes, Noel ^a   Chiprout, Eli ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATIONS.; CELL LIBRARIES; COMPUTER-AIDED DESIGN; CURRENT SOURCE; CURRENT SOURCE MODEL; DIGITAL APPLICATIONS; ELECTRICAL ANALYSIS; ELECTRICAL EFFECTS; ELECTRICAL MODELING; GATE LEVELS; INTERNATIONAL CONFERENCES; MACRO MODELING; MICROPROCESSOR DESIGNS; MODELING ACCURACY; MULTIPLE-INPUT SWITCHING; NEW APPROACHES; NEW MODEL; PORT CHARACTERIZATION; PROMISING TECHNIQUE; RUN-TIME;

ADMINISTRATIVE DATA PROCESSING; ANALOG TO DIGITAL CONVERSION; CELLS; CHLORINE COMPOUNDS; CYTOLOGY; DESIGN; DIGITAL ARITHMETIC; SWITCHING CIRCUITS; TIME MEASUREMENT;

ELECTRIC NETWORK ANALYSIS;

EID: 50249175154     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397344     Document Type: Conference Paper

References (24)

1. J. F. Croix and D. F. Wong, "Blade and Razor: Cell and interconnect delay analysis using current-based models," Proc. of DAC 2003, pp. 386-389.
2. I. Keller, K. Tseng, and N. Verghese, "A robust cell-level crosstalk delay change analysis," Proc. of ICCAD, pp. 147-154, Nov. 2004.
3. P. Li and E. Acar, "Waveform independent gate models for accurate timing analysis", Proc. ICCD, pp. 363-365, Oct. 2005.
4. C. Amin, C. Kashyap, N. Menezes, K. Killpack and E. Chiprout, "A multi-port current source model for multipleinput switching effects in CMOS library cells," Proc. of DAC, pp. 247-252, Jul. 2006.
5. C. Amin, F. Dartu, and Y. L Ismail, "Weibull based analytical waveform model," Proc. of ICCAD, pp. 161-168, Nov. 2005.
6. S. R. Nassif and E. Acar, "Advanced waveform models for the nanometer regime," Proc. of TAU, 2004.
7. J. C. Ebergen, S. Fairbanks, and I. E. Sutherland, "Predicting performance of micropipelines using Charlie diagrams," Proc. of Advanced Research in Async. Circuits and Systems, pp. 238-246, Mar. 1998.
8. V. Chandramouli and K. A. Sakallah, "Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time," Proc. of DAC, pp. 617-622, Jun. 1996.
9. L-C Chen, S. K. Gupta, M. A. Breuer, "A new gate delay model for simultaneous switching and its applications," Proc. of DAC, pp. 289-294, Jun. 2001.
10. J. Qian, S. Pullela, and L. Pillage, "Modeling the effective capacitance for the RC interconnect of CMOS gates," IEEE Trans. on CAD, vol. 13, no. 12, pp. 1526-1535, Dec. 1994.
11. F. Dartu, N. Menezes, and L. T. Pileggi, "Performance computation for precharacterized CMOS gates with RC loads," IEEE Trans. on CAD, vol. 15, no. 5, pp. 544-553, May 1996.
12. F. Dartu and L. T. Pileggi, "Calculating worst-case gate delays due to dominant capacitance coupling," Proc. of DAC, pp. 46-51, Jun. 1997.
13. L. T. Pillage and R. A. Rohrer, "Asymptotic waveform evaluation for static timing analysis," IEEE Trans. on CAD, vol. 9, no. 4, pp. 352-366, 1990.
14. A. Odabasioglu, M. Celik, and L. T. Pileggi, "PRIMA: Passive reduced order interconnect macromodeling algorithm," IEEE Trans. on CAD, vol. 17, no. 8, pp. 645-654, 1998.
15. P. Feldmann and R. W. Freund, "Efficient linear circuit analysis by Pade approximation via Lanczos process," IEEE Trans. on CAD, vol. 14, no. 5, pp. 639-649, 1995.
16. D. Blaauw, S. Sirichotiyakul, and C. Oh, "Driver modeling and alignment for worst-case delay noise," IEEE Trans. on VLSI, pp. 157-165, Apr. 2003.
17. M. Rewienski and J. White, "A trajectory piece-wise linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices," IEEE Trans. on CAD, vol. 22, no. 2, pp. 155-170, 2003.
18. N. Dong and J. Roychowdhury, "Automated nonlinear macromodeling of output buffers for high speed digital applications," Proc. of DAC, pp. 51-56, 2005.
19. "CCS timing white paper," Composite Current Source, Synopsys, [online] http://www.synopsys.com/products/solutions/galaxy/ccs/cc_source.html, 2005.
20. "Delay calculation meets the nanometer era," Cadence Technical Paper, [online] http://www.cadence.com/products/digital_ic/tech_info.aspx, 2005.
21. V. Veetil, D. Sylvester, and D. Blaauw, "Fast and accurate waveform analysis with current source models," Proc. of TA U, pp. 73-79, Feb. 2007.
22. L. W. Nagel, SPICE 2 - A computer to simulate semiconductor circuits, Memo. ERL-M520, University of California, Berkeley, 1975.
23. M. Celik, A. Odabasioglu, and L. Pileggi, IC Interconnect Analysis, Kluwer Academic Publishers, 2002.
24. M. Shoji, High Speed Digital Circuits, Addison-Wesley, 1996.