-
1
-
-
84964994951
-
-
K. Mohanram and N. Touba. Partial error masking to reduce soft error failure rate in logic circuits, in 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, 2003, pp. 433-440.
-
K. Mohanram and N. Touba. "Partial error masking to reduce soft error failure rate in logic circuits," in 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, 2003, pp. 433-440.
-
-
-
-
2
-
-
29344459216
-
Design for soft error mitigation
-
M. Nicolaidis, "Design for soft error mitigation," IEEE Trans. on Device and Materials Reliability, vol. 5, no. 3, pp. 405-418, 2005.
-
(2005)
IEEE Trans. on Device and Materials Reliability
, vol.5
, Issue.3
, pp. 405-418
-
-
Nicolaidis, M.1
-
3
-
-
33846595665
-
Sequential element design with built-in soft error resilience
-
M. Zhang, S. Mitra, T. Mak, N. Seifert, N. Wang, Q. Shi, K. Kim, N. Shanbhag, and S. Patel, "Sequential element design with built-in soft error resilience," IEEE Trans. on VLSI, vol. 14, no. 12, pp. 1368-1378, 2006.
-
(2006)
IEEE Trans. on VLSI
, vol.14
, Issue.12
, pp. 1368-1378
-
-
Zhang, M.1
Mitra, S.2
Mak, T.3
Seifert, N.4
Wang, N.5
Shi, Q.6
Kim, K.7
Shanbhag, N.8
Patel, S.9
-
4
-
-
34548308773
-
Verification-guided soft error resilience
-
Nice, France
-
S. Seshia, W. Li, and S. Mitra, "Verification-guided soft error resilience," in 2007 Design, Automation and Test in Europe Conference and Exposition (DATE 2007), April 16-20, 2007, Nice, France, 2007.
-
(2007)
2007 Design, Automation and Test in Europe Conference and Exposition (DATE 2007), April 16-20, 2007
-
-
Seshia, S.1
Li, W.2
Mitra, S.3
-
5
-
-
0142184763
-
-
K. Mohanram and N. Touba. Cost-effective approach for reducing soft error failure rate in logic circuits, in Proceedings 2003 International Test Conference (ITC 2003), 28 September - 3 October 2003, Charlotte, NC, USA, 2003, pp. 893-901.
-
K. Mohanram and N. Touba. "Cost-effective approach for reducing soft error failure rate in logic circuits," in Proceedings 2003 International Test Conference (ITC 2003), 28 September - 3 October 2003, Charlotte, NC, USA, 2003, pp. 893-901.
-
-
-
-
6
-
-
24344478598
-
Soft-spot analysis: Targeting compund noise effects in nanometer circuits
-
C. Zhao, S. Dey, and X. Bai, "Soft-spot analysis: Targeting compund noise effects in nanometer circuits," IEEE Design & Test of Comp., vol. 22, no. 4, pp. 362-375, 2005.
-
(2005)
IEEE Design & Test of Comp
, vol.22
, Issue.4
, pp. 362-375
-
-
Zhao, C.1
Dey, S.2
Bai, X.3
-
7
-
-
34247253351
-
Combinational logic soft error analysis and protection
-
Como. Italy
-
A. Nieuwland, S. Jasarevic, and G. Jerin, "Combinational logic soft error analysis and protection," in 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como. Italy, 2006.
-
(2006)
12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006
-
-
Nieuwland, A.1
Jasarevic, S.2
Jerin, G.3
-
8
-
-
37549071089
-
-
J. Hayes, I. Polian, and B. Becker. An analysis framework for transient-error tolerance, in 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, 2007, pp. 249-255.
-
J. Hayes, I. Polian, and B. Becker. "An analysis framework for transient-error tolerance," in 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, 2007, pp. 249-255.
-
-
-
-
9
-
-
52049098927
-
A refined electrical model for particle strikes and its impact on SEU prediction
-
Rome, Italy
-
S. Hellebrand, C. Zoellin, H.-J. Wunderlich, S. Ludwig. T. Coym, and B. Straube, "A refined electrical model for particle strikes and its impact on SEU prediction." in 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy, 2007.
-
(2007)
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007
-
-
Hellebrand, S.1
Zoellin, C.2
Wunderlich, H.-J.3
Ludwig, S.4
Coym, T.5
Straube, B.6
-
10
-
-
34547168080
-
A design approach for radiation-hard digital electronics
-
San Francisco, CA, USA, July 24-28
-
R. Garg. N. Jayakumar. S. Khatri, and G. Choi, "A design approach for radiation-hard digital electronics," in Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, 2006, pp. 773-778.
-
(2006)
Proceedings of the 43rd Design Automation Conference, DAC 2006
, pp. 773-778
-
-
Garg, R.1
Jayakumar, N.2
Khatri, S.3
Choi, G.4
-
11
-
-
34548306672
-
Accurate and scalable reliability analysis of logic circuits
-
France
-
M. Choudhury and K. Mohanram. "Accurate and scalable reliability analysis of logic circuits," in 2007 Design, Automation and Test in Eumpe Conference and Exposition (DATE 2007), April 16-20, 2007. Nice, France, 2007, pp. 1454-1459.
-
(2007)
2007 Design, Automation and Test in Eumpe Conference and Exposition (DATE 2007), April 16-20, 2007. Nice
, pp. 1454-1459
-
-
Choudhury, M.1
Mohanram, K.2
-
13
-
-
29344470310
-
Physics-based simulation of single-event effects
-
P. Dodd, "Physics-based simulation of single-event effects," IEEE Trans. on Device and Materials Reliability, vol. 5, no. 3, pp. 343-357, 2005.
-
(2005)
IEEE Trans. on Device and Materials Reliability
, vol.5
, Issue.3
, pp. 343-357
-
-
Dodd, P.1
-
14
-
-
0031373956
-
Attenuation of single event induced pulses in CMOS combinational logic
-
M. Baze and S. Buchner, "Attenuation of single event induced pulses in CMOS combinational logic," IEEE Trans. on Nuclear Science, vol. 44, no. 6, pp. 2217-2223, 1997.
-
(1997)
IEEE Trans. on Nuclear Science
, vol.44
, Issue.6
, pp. 2217-2223
-
-
Baze, M.1
Buchner, S.2
-
15
-
-
0026400768
-
Simulation of SEU transients in CMOS ICs
-
N. Kaul, B. Bhuva, and S. Kerns, "Simulation of SEU transients in CMOS ICs," IEEE Trans. on Nuclear Science, vol. 38, no. 6, pp. 1514-1520, 1991.
-
(1991)
IEEE Trans. on Nuclear Science
, vol.38
, Issue.6
, pp. 1514-1520
-
-
Kaul, N.1
Bhuva, B.2
Kerns, S.3
-
16
-
-
24944449662
-
Accurate estimation of soft error rate (SER) in VLSI circuits
-
Cannes, France
-
A. Maheshwari, I. Koren, and W. Burleson, "Accurate estimation of soft error rate (SER) in VLSI circuits," in 19th IEEE International Symposium on Defect and Fault Tolerance In VLSI Systems (DFT04), 10-13 October 2004, Cannes, France, 2004.
-
(2004)
19th IEEE International Symposium on Defect and Fault Tolerance In VLSI Systems (DFT04), 10-13 October 2004
-
-
Maheshwari, A.1
Koren, I.2
Burleson, W.3
-
18
-
-
11044239423
-
Production and propagation of single-event transients in high-speed digital logic ICs
-
P. Dodd, "Production and propagation of single-event transients in high-speed digital logic ICs," IEEE Trans. on Nuclear Science, vol. 51, no. 6, pp. 3278-3284, 2004.
-
(2004)
IEEE Trans. on Nuclear Science
, vol.51
, Issue.6
, pp. 3278-3284
-
-
Dodd, P.1
-
19
-
-
0020091827
-
Alpha-particle-induced field and enhanced collection of carriers
-
C. Hu, "Alpha-particle-induced field and enhanced collection of carriers," IEEE Electron Device Letters, vol. 3, no. 2, pp. 31-34, 1982.
-
(1982)
IEEE Electron Device Letters
, vol.3
, Issue.2
, pp. 31-34
-
-
Hu, C.1
-
20
-
-
0020312672
-
Charge funneling in N-und P-type Si substrates
-
F. McLean and T. Oldham, "Charge funneling in N-und P-type Si substrates," IEEE Trans. on Nuclear Science, vol. 29, no. 6, pp. 2018-2023, 1982.
-
(1982)
IEEE Trans. on Nuclear Science
, vol.29
, Issue.6
, pp. 2018-2023
-
-
McLean, F.1
Oldham, T.2
-
21
-
-
0020298427
-
Collection of charge on junction nodes from ion tracks
-
G. Messenger, "Collection of charge on junction nodes from ion tracks," IEEE Trans. on Nuclear Science, vol. 29, no. 6, pp. 2024-2031, 1982.
-
(1982)
IEEE Trans. on Nuclear Science
, vol.29
, Issue.6
, pp. 2024-2031
-
-
Messenger, G.1
-
22
-
-
0027800753
-
An analysis of path sensitization criteria
-
Cambridge, MA, USA, October 3-6
-
J. P. M. Silva and K. A. Sakallah, "An analysis of path sensitization criteria," in Proceedings International Conference on Computer Design, ICCD '93, Cambridge, MA, USA, October 3-6, 1993, 1993, pp. 68-72.
-
(1993)
Proceedings International Conference on Computer Design, ICCD '93
, pp. 68-72
-
-
Silva, J.P.M.1
Sakallah, K.A.2
-
23
-
-
46149091986
-
Soft error derating computation in sequential circuits
-
San Jose, CA, USA
-
H. Asadi and M. B. Tahoori, "Soft error derating computation in sequential circuits," in 2006 International Conference on Computer-Aided Design (ICCAD'06). November 5-9, 2006, San Jose, CA, USA, 2006, pp. 497-501.
-
(2006)
2006 International Conference on Computer-Aided Design (ICCAD'06). November 5-9, 2006
, pp. 497-501
-
-
Asadi, H.1
Tahoori, M.B.2
-
24
-
-
0022252326
-
PROTEST: A tool for probabilistic testability analysis
-
Las Vegas, Nevada, USA
-
H.-J. Wunderlich, "PROTEST: A tool for probabilistic testability analysis," in Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985.
-
(1985)
Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985
-
-
Wunderlich, H.-J.1
-
25
-
-
26044461787
-
A testability metric for path delay faults and its application
-
Yokohama, Japan
-
H. Tsai, K.Cheng, and V. Agrawal, "A testability metric for path delay faults and its application," in Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan, 2000, pp. 593-598.
-
(2000)
Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000
, pp. 593-598
-
-
Tsai, H.1
Cheng, K.2
Agrawal, V.3
-
26
-
-
0021574326
-
Applications of testability analysis: From ATPG to critical delay path tracing
-
Philadelphia. PA, USA, October
-
F. Brglez, P. Pownall. and R. Hum, "Applications of testability analysis: From ATPG to critical delay path tracing," in Proceedings International Test Conference 1984, Philadelphia. PA, USA, October 1984, 1984, pp. 705-712.
-
(1984)
Proceedings International Test Conference 1984
, pp. 705-712
-
-
Brglez, F.1
Pownall, P.2
Hum, R.3
-
27
-
-
0027794338
-
A BDD-based algorithm for computation of exact fault detection probabilities
-
Toulouse, France
-
R. Krieger, B. Becker, and R. Sinkovic, "A BDD-based algorithm for computation of exact fault detection probabilities." in 23rd Annual International Symposium on Fault-Tolerant Computing, June 22-24, 1993, Toulouse, France, 1993. pp. 186-195.
-
(1993)
23rd Annual International Symposium on Fault-Tolerant Computing, June 22-24, 1993
, pp. 186-195
-
-
Krieger, R.1
Becker, B.2
Sinkovic, R.3
-
28
-
-
0036605167
-
An FPGA-based approach for speeding-up fault injection campaigns on safety-critical circuits
-
P. Civera, L. Macchiarulo, M. Rebaudengo, M. S. Reorda, and M. Violante, "An FPGA-based approach for speeding-up fault injection campaigns on safety-critical circuits," Journal of Electronic Testing: Theory and Applications, vol. 18, no. 3, pp. 261-271, 2002.
-
(2002)
Journal of Electronic Testing: Theory and Applications
, vol.18
, Issue.3
, pp. 261-271
-
-
Civera, P.1
Macchiarulo, L.2
Rebaudengo, M.3
Reorda, M.S.4
Violante, M.5
-
29
-
-
33646902164
-
-
S. Krishnuswamy, G. Viamontes, I. Markov, and J. Hayes, Accurate reliability evaluation and enhancement via probabilistic transfer matrices. in 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, 2005, pp. 282-287.
-
S. Krishnuswamy, G. Viamontes, I. Markov, and J. Hayes, "Accurate reliability evaluation and enhancement via probabilistic transfer matrices." in 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, 2005, pp. 282-287.
-
-
-
-
30
-
-
33748331354
-
Soft error-rate analysis (SERA) methodology
-
M. Zhang and N. Shunbhag, "Soft error-rate analysis (SERA) methodology." IEEE Trans. on CAD, vol. 25, no. 10, pp. 2140-2155, 2006.
-
(2006)
IEEE Trans. on CAD
, vol.25
, Issue.10
, pp. 2140-2155
-
-
Zhang, M.1
Shunbhag, N.2
-
31
-
-
46749136822
-
-
C. Rusu, A. Bougerai, L. Anghel, C. Weulerse, N. Buard, S. Benhammadi, N. Renaud, G. Hubert, F. Wrobel, T. Carriere, and R. Gaillard, Multiple event transient induced by nuclear reactions in CMOS logic cells, in 13th IEEE International On-Line Testing Symposium (IOLTS 2007). 8-11 July 2007. Heraklion. Crete, Greece, 2007, pp. 137-145.
-
C. Rusu, A. Bougerai, L. Anghel, C. Weulerse, N. Buard, S. Benhammadi, N. Renaud, G. Hubert, F. Wrobel, T. Carriere, and R. Gaillard, "Multiple event transient induced by nuclear reactions in CMOS logic cells," in 13th IEEE International On-Line Testing Symposium (IOLTS 2007). 8-11 July 2007. Heraklion. Crete, Greece, 2007, pp. 137-145.
-
-
-
-
33
-
-
0027848063
-
A logic-level model for α-particle hits in CMOS circuits
-
International Conference on Computer Design, ICCD '93, Cambridge, MA, USA, October 3-6
-
H. Cha and J. Patel, "A logic-level model for α-particle hits in CMOS circuits," in International Conference on Computer Design, ICCD '93, Cambridge, MA, USA, October 3-6, 1993, ser. 538-542, 1993.
-
(1993)
ser
, vol.538-542
-
-
Cha, H.1
Patel, J.2
-
34
-
-
51549104071
-
-
K. McElvain, IWLS'93 benchmark set: Version 4.0, in Int'l Workshop on Logic Synth, 1993
-
K. McElvain, "IWLS'93 benchmark set: Version 4.0," in Int'l Workshop on Logic Synth., 1993.
-
-
-
|