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Volumn , Issue , 2007, Pages 1297-1300

Adaptive SRAM design for dynamic voltage scaling VLSI systems

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; ENERGY CONSERVATION; LOGIC DESIGN; VOLTAGE STABILIZING CIRCUITS;

EID: 51449091991     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2007.4488788     Document Type: Conference Paper
Times cited : (31)

References (11)
  • 4
    • 13944271662 scopus 로고    scopus 로고
    • Ultra-Low-Power Design: Device and Logic Design Approaches
    • E. Macii, Ed. Kluwer Academic Press
    • C. Heer and U. Schlichtmann, "Ultra-Low-Power Design: Device and Logic Design Approaches," in Ultra Low-Power Electronics and Design, E. Macii, Ed. Kluwer Academic Press, 2004.
    • (2004) Ultra Low-Power Electronics and Design
    • Heer, C.1    Schlichtmann, U.2
  • 5
    • 29144483477 scopus 로고    scopus 로고
    • Analysis of Energy Reduction on Dynamic Voltage Scaling-Enabled Systems
    • Dec
    • L. Yuan and G. Qu, "Analysis of Energy Reduction on Dynamic Voltage Scaling-Enabled Systems," IEEE Trans. Computer-aided Design, vol. 24, no. 12, pp. 1827-1837, Dec. 2005.
    • (2005) IEEE Trans. Computer-aided Design , vol.24 , Issue.12 , pp. 1827-1837
    • Yuan, L.1    Qu, G.2
  • 8
    • 33746369469 scopus 로고    scopus 로고
    • Static Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS
    • July
    • B. Calhoun and A. Chandrakasan, "Static Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS," IEEE Journal of Solid-state Circuits, vol. 41, pp. 1673-1679, July 2006.
    • (2006) IEEE Journal of Solid-state Circuits , vol.41 , pp. 1673-1679
    • Calhoun, B.1    Chandrakasan, A.2
  • 10
    • 25144514874 scopus 로고    scopus 로고
    • Modeling and Sizing for Minimum Energy Operation in Subthreshold Circuits
    • Sept
    • B. H. Calhoun, A. Wang, and A. Chandrakasan, "Modeling and Sizing for Minimum Energy Operation in Subthreshold Circuits," IEEE Journal of Solid-state Circuits, vol. 40, no. 9, pp. 1778-1786, Sept. 2005.
    • (2005) IEEE Journal of Solid-state Circuits , vol.40 , Issue.9 , pp. 1778-1786
    • Calhoun, B.H.1    Wang, A.2    Chandrakasan, A.3
  • 11
    • 37849187098 scopus 로고    scopus 로고
    • Adaptive Ratio-Size Gates for Minimum Energy Operation
    • Nov
    • S. Kirolos and Y. Massoud, "Adaptive Ratio-Size Gates for Minimum Energy Operation," IEEE Trans. Circuits and Systems II, vol. 53, no. 11, Nov. 2006.
    • (2006) IEEE Trans. Circuits and Systems II , vol.53 , Issue.11
    • Kirolos, S.1    Massoud, Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.