Modeling and estimation of leakage in sub-90nm devices

Proceedings of the IEEE International Conference on VLSI Design

Volumn 17, Issue , 2004, Pages 65-70

  Raychowdhury, Arijit ^a   Mukhopadhyay, Saibal ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT DENSITY; DOPING (ADDITIVES); ELECTRIC FIELDS; ELECTRICAL ENGINEERING; ELECTRON TUNNELING; LEAKAGE CURRENTS; MATHEMATICAL MODELS; MOSFET DEVICES; PROBABILITY; THRESHOLD VOLTAGE; TRANSISTORS;

LEAKAGE ESTIMATION; SHORT CHANNEL EFFECTS (SCE); SUPPLY VOLTAGE; TUNNELING CURRENTS;

CMOS INTEGRATED CIRCUITS;

EID: 2342535060     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. K. Roy,etal, Proceeding of IEEE, Feb, 2003.
2. Y. Taur etal., Fundamentals of Modern VLSI Devices, New York, USA: Cambridge University Press, 1998, ch.2, pp. 94-97.
3. S.Mukhopadhyay, etal., DAC, 2003, pp. 169-174.
4. "Well-Tempered" Balk-Si NMOSFET Device Home Page, http:/www-mtl.tnit.edu/Well/
5. MEDICI: Two-Dimensional Semiconductor Device Simulation Program, AVANT! Corp., Fremont, CA, 2000.