Three subthreshold flip-flop cells characterized in 90 nm and 65 nm CMOS technology

Proceedings - 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS

Volumn , Issue , 2008, Pages 8-11

  Alstad, Håvard Pedersen ^a   Aunet, Snorre ^a  

^a UNIVERSITY OF OSLO   (Norway)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; DESIGN; ELECTRON TUBES; EPITAXIAL GROWTH; INTEGRATED CIRCUIT LAYOUT;

ELECTRONIC CIRCUITS; PROCESS VARIATIONS; SUPPLY VOLTAGES;

FLIP FLOP CIRCUITS;

EID: 50649092223     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DDECS.2008.4538745     Document Type: Conference Paper

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