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Volumn , Issue , 2007, Pages

Seven subthreshold flip-flop cells

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGIES; COMPARATIVE STUDIES; D FLIP FLOPS; POWER DISSIPATIONS; SUB THRESHOLD REGION; SUB THRESHOLDS; SUPPLY VOLTAGES; ULTRA-LOW-POWER;

EID: 50249115521     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NORCHP.2007.4481061     Document Type: Conference Paper
Times cited : (11)

References (16)
  • 2
    • 0015330654 scopus 로고
    • Ion-implanted complementary MOS transistors in low-voltage circuits
    • 7
    • Swanson, R.M., Meindl, J.D.: Ion-implanted complementary MOS transistors in low-voltage circuits. IEEE J. S.-S. C. 7 (1972) 146-153
    • (1972) IEEE J. S.-S , vol.100 , pp. 146-153
    • Swanson, R.M.1    Meindl, J.D.2
  • 3
    • 0035242870 scopus 로고    scopus 로고
    • Robust subthreshold logic for ultra-low power operation
    • Soeleinan. H., Roy. K., Paul, B.C.: Robust subthreshold logic for ultra-low power operation. IEEE Tran. on VLSI Systems 9 (2001) 90-99
    • (2001) IEEE Tran. on VLSI Systems , vol.9 , pp. 90-99
    • Soeleinan, H.1    Roy, K.2    Paul, B.C.3
  • 4
    • 0026124101 scopus 로고
    • Current-mode subthreshold MOS circuits for analog VLSI neural systems
    • Andreou, A.G., et al.: Current-mode subthreshold MOS circuits for analog VLSI neural systems. IEEE T. Neural Netw. 2 (1991) 205-213
    • (1991) IEEE T. Neural Netw , vol.2 , pp. 205-213
    • Andreou, A.G.1
  • 6
    • 62949137157 scopus 로고    scopus 로고
    • Xue, S., Oelmann, B.: Comparative study of low-voltage performance of standard-cell flip-flops. Proc. of IEEE ICECS 2001 2 (2001) 953-957
    • Xue, S., Oelmann, B.: Comparative study of low-voltage performance of standard-cell flip-flops. Proc. of IEEE ICECS 2001 2 (2001) 953-957
  • 8
    • 0022795057 scopus 로고
    • Clocking schemes for high-speed digital systems
    • Unger, S.H., Tan, C.J.: Clocking schemes for high-speed digital systems. IEEE Trans. Comput. C-35 (1986) 880-895
    • (1986) IEEE Trans. Comput , vol.C-35 , pp. 880-895
    • Unger, S.H.1    Tan, C.J.2
  • 11
    • 0028733872 scopus 로고
    • A 2.2 W, 80 MHz superscalar RISC microprocessor.
    • Gerosa, G., et al.: A 2.2 W, 80 MHz superscalar RISC microprocessor. IEEE J. Solid-State Circuits 29 (1994) 1440-1452
    • (1994) IEEE J. Solid-State Circuits , vol.29 , pp. 1440-1452
    • Gerosa, G.1
  • 12
    • 0023436314 scopus 로고    scopus 로고
    • A true single-phase-clock dynamic CMOS circuit technique
    • SC-22
    • Yuan, J.R., Karlsson, I., Svensson, C.: A true single-phase-clock dynamic CMOS circuit technique. IEEE J. S.-S. C. SC-22 (87) 899-901
    • IEEE J. S.-S , vol.100 , Issue.87 , pp. 899-901
    • Yuan, J.R.1    Karlsson, I.2    Svensson, C.3
  • 14
    • 11944273157 scopus 로고    scopus 로고
    • A 180 mV subthreshold FFT processor using a minimum energy design methodology
    • Wang, A., Chandrakasan, A.: A 180 mV subthreshold FFT processor using a minimum energy design methodology. IEEE J. Solid-State Circuits 40 (2005) 310-319
    • (2005) IEEE J. Solid-State Circuits , vol.40 , pp. 310-319
    • Wang, A.1    Chandrakasan, A.2
  • 16
    • 25144514874 scopus 로고    scopus 로고
    • Modeling and sizing for minimum energy operation in subthreshold circuits
    • Calhoun, B.H., Wang. A., Chandrakasan, A.: Modeling and sizing for minimum energy operation in subthreshold circuits. IEEE J. Solid-State Circuits 40 (2005) 1778-1786
    • (2005) IEEE J. Solid-State Circuits , vol.40 , pp. 1778-1786
    • Calhoun, B.H.1    Wang, A.2    Chandrakasan, A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.