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Volumn , Issue , 2007, Pages 1173-1176

Comparative analysis of ultra-low voltage flip-flops for energy efficiency

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENCY; PROBLEM SOLVING; SWITCHING THEORY; TRIGGER CIRCUITS; VOLTAGE REGULATORS;

EID: 34548842265     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (6)

References (12)
  • 1
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    • B. Zhai, D. Blauuw, and K. Flautner, "Theoretical and practical limits of dynamic voltage scaling," in Proc. DAC'04, pp. 868-873, Sept. 2004.
    • (2004) Proc. DAC'04 , pp. 868-873
    • Zhai, B.1    Blauuw, D.2    Flautner, K.3
  • 3
    • 33947136855 scopus 로고    scopus 로고
    • Computing with subthreshold leakage: Device/circuit/architecture co-design for ultra low-power subthreshold operation
    • Nov
    • A. Raychowdhury, B. Paul, S. Bhunia, and K. Roy, "Computing with subthreshold leakage: device/circuit/architecture co-design for ultra low-power subthreshold operation," IEEE Transactions on VLSI Systems, pp. 1213-1224, Nov. 2005.
    • (2005) IEEE Transactions on VLSI Systems , pp. 1213-1224
    • Raychowdhury, A.1    Paul, B.2    Bhunia, S.3    Roy, K.4
  • 4
    • 0033116422 scopus 로고    scopus 로고
    • Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
    • Apr
    • V. Stojanovic and V. Oklobdzija, "Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems," IEEE J. Solid-State Circuits, vol. 34, pp. 536-548, Apr. 1999.
    • (1999) IEEE J. Solid-State Circuits , vol.34 , pp. 536-548
    • Stojanovic, V.1    Oklobdzija, V.2
  • 5
    • 84951809300 scopus 로고    scopus 로고
    • Activity-sensitive flip-flop and latch selection for reduce energy
    • Advanced Research in VLSI, pp, Mar
    • S. Heo, R. Krashinsky, and K. Asanovic, "Activity-sensitive flip-flop and latch selection for reduce energy," in Proc. 19th Conf. Advanced Research in VLSI, pp 59-74, Mar. 2001.
    • (2001) Proc. 19th Conf , pp. 59-74
    • Heo, S.1    Krashinsky, R.2    Asanovic, K.3
  • 6
    • 33847211913 scopus 로고    scopus 로고
    • Characterizing dynamic and leakage power behavior in flip-flops
    • Sep
    • R. Ramanarayanan, N. Vijaykrishnan and M. J Irwin, "Characterizing dynamic and leakage power behavior in flip-flops," in Proc. ASIC/SOC'02, pp. 433-437, Sep. 2002.
    • (2002) Proc. ASIC/SOC'02 , pp. 433-437
    • Ramanarayanan, R.1    Vijaykrishnan, N.2    Irwin, M.J.3
  • 7
    • 26044475921 scopus 로고    scopus 로고
    • Noise metrics in flip-flop designs
    • July
    • M. Elgamel, M. I. Faisal, and M. A. Bayoumi, "Noise metrics in flip-flop designs," IEICE Trans. Inf. Syst., vol. E88-D, pp. 1501-1505, July 2005.
    • (2005) IEICE Trans. Inf. Syst , vol.E88-D , pp. 1501-1505
    • Elgamel, M.1    Faisal, M.I.2    Bayoumi, M.A.3
  • 9
    • 0028733872 scopus 로고
    • A 2.2 W, 80 MHz superscalar RISC microprocessor
    • Dec
    • G. Gerosa et. al, "A 2.2 W, 80 MHz superscalar RISC microprocessor," IEEE J. Solid-State Circuits, vol. 29, pp. 1440-1452, Dec. 1994.
    • (1994) IEEE J. Solid-State Circuits , vol.29 , pp. 1440-1452
    • Gerosa, G.1    et., al.2
  • 10
    • 0030083355 scopus 로고    scopus 로고
    • Flow-through latch and edge-triggered flip-flop hybrid elements
    • Feb
    • H. Partovi et al., "Flow-through latch and edge-triggered flip-flop hybrid elements," in Proc. ISSCC'96, pp. 138-139, Feb. 1996.
    • (1996) Proc. ISSCC'96 , pp. 138-139
    • Partovi, H.1
  • 11
    • 0030285348 scopus 로고    scopus 로고
    • A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor
    • Nov
    • J. Montanaro et al., "A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor," IEEE J. Solid-State Circuits, vol. 31, pp. 1703-1714, Nov. 1996.
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    • Montanaro, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.