메뉴 건너뛰기




Volumn 52, Issue 9, 2008, Pages 1345-1352

Single-grain Si thin-film transistors SPICE model, analog and RF circuit applications

Author keywords

Czochralski process; BSIMSOI modified model; Operational amplifier; RF amplifier; Single grain thin film transistor; Voltage reference

Indexed keywords

AMPLIFIERS (ELECTRONIC); ANALOG CIRCUITS; CELLULAR RADIO SYSTEMS; CMOS INTEGRATED CIRCUITS; DENSITY (SPECIFIC GRAVITY); ELECTRIC CURRENT REGULATORS; ELECTRONICS ENGINEERING; FREQUENCY CONVERTER CIRCUITS; GARNETS; NETWORKS (CIRCUITS); OPERATIONAL AMPLIFIERS; OPTICAL DESIGN; POWER SUPPLY CIRCUITS; SEMICONDUCTING ORGANIC COMPOUNDS; SILICON; TECHNOLOGY; THIN FILM DEVICES; THIN FILM TRANSISTORS; TRANSISTORS;

EID: 50349094812     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2008.04.004     Document Type: Article
Times cited : (4)

References (18)
  • 1
    • 29244431688 scopus 로고    scopus 로고
    • Dependence of single-crystalline Si TFT characteristics on the channel position inside a location-controlled grain
    • Rana V., Ishihara R., Hiroshima Y., Abe D., Inoue S., Shimoda T., et al. Dependence of single-crystalline Si TFT characteristics on the channel position inside a location-controlled grain. IEEE Trans Electron Dev 51 12 (2005) 2622-2628
    • (2005) IEEE Trans Electron Dev , vol.51 , Issue.12 , pp. 2622-2628
    • Rana, V.1    Ishihara, R.2    Hiroshima, Y.3    Abe, D.4    Inoue, S.5    Shimoda, T.6
  • 2
    • 10444261087 scopus 로고    scopus 로고
    • High performance p-channel single-crystalline Si TFTs fabricated inside a location-controlled grain by μ-Czochralski process
    • Rana V., Ishihara R., Metselaar W., Beenakker K., Hiroshima Y., Abe D., et al. High performance p-channel single-crystalline Si TFTs fabricated inside a location-controlled grain by μ-Czochralski process. IEICE Trans Electron E87-C 11 (2004) 1943-1947
    • (2004) IEICE Trans Electron , vol.E87-C , Issue.11 , pp. 1943-1947
    • Rana, V.1    Ishihara, R.2    Metselaar, W.3    Beenakker, K.4    Hiroshima, Y.5    Abe, D.6
  • 3
    • 0035903422 scopus 로고    scopus 로고
    • Formation of location-controlled crystalline islands using substrate-embedded-seeds in excimer-laser crystallization of silicon film
    • van der Wilt P.C., van Dijk B.D., Bertens G.J., Ishihara R., and Beenakker K. Formation of location-controlled crystalline islands using substrate-embedded-seeds in excimer-laser crystallization of silicon film. Appl Phys Lett 72 12 (2001) 1819-1822
    • (2001) Appl Phys Lett , vol.72 , Issue.12 , pp. 1819-1822
    • van der Wilt, P.C.1    van Dijk, B.D.2    Bertens, G.J.3    Ishihara, R.4    Beenakker, K.5
  • 4
    • 44849120153 scopus 로고    scopus 로고
    • Saputra N, Danesh M, Baiano A, Ishihara R, Long JR, Metselaar JW et al. Single-grain Si thin-film transistors for analog and RF circuit applications. In: Proceeding of the ESSDERC 2007 conference, Munich, Germany; September 2007. p. 107-10.
    • Saputra N, Danesh M, Baiano A, Ishihara R, Long JR, Metselaar JW et al. Single-grain Si thin-film transistors for analog and RF circuit applications. In: Proceeding of the ESSDERC 2007 conference, Munich, Germany; September 2007. p. 107-10.
  • 5
    • 34547599226 scopus 로고    scopus 로고
    • Polysilicon high frequency devices for large area electronics: characterization, simulation and modeling
    • Botrel J.L., Savry O., Rozeau O., Templier F., and Jomaah J. Polysilicon high frequency devices for large area electronics: characterization, simulation and modeling. Thin Solid Films 515 19 (2007) 7422-7427
    • (2007) Thin Solid Films , vol.515 , Issue.19 , pp. 7422-7427
    • Botrel, J.L.1    Savry, O.2    Rozeau, O.3    Templier, F.4    Jomaah, J.5
  • 6
    • 33744758663 scopus 로고    scopus 로고
    • High-speed mechanically flexible single-crystal silicon thin-film transistors on plastic substrates
    • Ahn J.-H., Kim H.-S., Lee K.J., Zhu Z., Menard E., Nuzzo R.G., et al. High-speed mechanically flexible single-crystal silicon thin-film transistors on plastic substrates. IEEE Electron Dev Lett 27 June (2006) 460-462
    • (2006) IEEE Electron Dev Lett , vol.27 , Issue.June , pp. 460-462
    • Ahn, J.-H.1    Kim, H.-S.2    Lee, K.J.3    Zhu, Z.4    Menard, E.5    Nuzzo, R.G.6
  • 7
    • 33846781308 scopus 로고    scopus 로고
    • Microstructure characterisation of location-controlled Si-islands crystallised by excimer laser in the μ-Czochralski (grain filter) process
    • Ishihara R., Danciu D., Tichelaar F., He M., Hiroshima Y., Inoue S., et al. Microstructure characterisation of location-controlled Si-islands crystallised by excimer laser in the μ-Czochralski (grain filter) process. J Cryst Growth 299 2 (2007) 316-321
    • (2007) J Cryst Growth , vol.299 , Issue.2 , pp. 316-321
    • Ishihara, R.1    Danciu, D.2    Tichelaar, F.3    He, M.4    Hiroshima, Y.5    Inoue, S.6
  • 8
    • 22944465043 scopus 로고    scopus 로고
    • Electrical property of coincidence site lattice grain boundary in location-controlled Si island by excimer-laser crystallization
    • Ishihara R., He M., Rana V., Hiroshima Y., Inoue S., Shimoda T., et al. Electrical property of coincidence site lattice grain boundary in location-controlled Si island by excimer-laser crystallization. Thin Solid Film 487 1-2 (2005) 97-101
    • (2005) Thin Solid Film , vol.487 , Issue.1-2 , pp. 97-101
    • Ishihara, R.1    He, M.2    Rana, V.3    Hiroshima, Y.4    Inoue, S.5    Shimoda, T.6
  • 9
    • 43349088786 scopus 로고    scopus 로고
    • Matsuki N, Ishihara R, Baiano A, Hiroshima Y, Inoue S, Beenakker CIM. Local electrical property of coincidence site-lattice boundary in location-controlled silicon islands by scanning spread resistance microscopy. In: International display workshop; 2007. p. 489-92.
    • Matsuki N, Ishihara R, Baiano A, Hiroshima Y, Inoue S, Beenakker CIM. Local electrical property of coincidence site-lattice boundary in location-controlled silicon islands by scanning spread resistance microscopy. In: International display workshop; 2007. p. 489-92.
  • 11
    • 0016597193 scopus 로고
    • The electrical properties of polycrystalline silicon films
    • Seto J.Y.W. The electrical properties of polycrystalline silicon films. J Appl Phys 46 12 (1975) 5247-5254
    • (1975) J Appl Phys , vol.46 , Issue.12 , pp. 5247-5254
    • Seto, J.Y.W.1
  • 13
    • 0031210179 scopus 로고    scopus 로고
    • SPICE models for amorphous silicon and polysilicon thin film transistors
    • Shur M.S., Slade H.C., Jancuski M.D., Owusu A.A., and Ytterdal T. SPICE models for amorphous silicon and polysilicon thin film transistors. J Electrochem Soc 144 8 (1997) 2833-2839
    • (1997) J Electrochem Soc , vol.144 , Issue.8 , pp. 2833-2839
    • Shur, M.S.1    Slade, H.C.2    Jancuski, M.D.3    Owusu, A.A.4    Ytterdal, T.5
  • 14
    • 50349101554 scopus 로고    scopus 로고
    • Level 62 RPI Poly-Si TFT Model, .
    • Level 62 RPI Poly-Si TFT Model, .
  • 15
    • 50349101364 scopus 로고    scopus 로고
    • BSIMSOI model, .
    • BSIMSOI model, .
  • 16
    • 0023576614 scopus 로고    scopus 로고
    • van Wijnen PJ, Claessen HR, Wolsheimer EA. A new straightforward calibration and correction procedure for on wafer high frequency S-parameter measurements (45 MHz-18 GHz). IEEE Bipolar Circ Technol Meeting Tech Dig; 1987. p. 70-3.
    • van Wijnen PJ, Claessen HR, Wolsheimer EA. A new straightforward calibration and correction procedure for on wafer high frequency S-parameter measurements (45 MHz-18 GHz). IEEE Bipolar Circ Technol Meeting Tech Dig; 1987. p. 70-3.
  • 18
    • 0036454666 scopus 로고    scopus 로고
    • Adriaensen S, Dessard V, Flandre D. A voltage reference compatible with standard SOI CMOS process and consuming 1 pA to 50 nA from room temperature up to 300 °C. IEEE Int SOI Conf Tech Dig; 2002. p. 130-1.
    • Adriaensen S, Dessard V, Flandre D. A voltage reference compatible with standard SOI CMOS process and consuming 1 pA to 50 nA from room temperature up to 300 °C. IEEE Int SOI Conf Tech Dig; 2002. p. 130-1.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.