A voltage reference compatible with standard SOI CMOS processes and consuming 1pA to 50nA from room temperature up to 300°C

IEEE International SOI Conference

Volumn , Issue , 2002, Pages 130-131

  Adriaensen, S ^a   Dessard, V ^b   Flandre, D ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^b CISSOID SA   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; ENERGY GAP; GATES (TRANSISTOR); MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY; THERMAL NOISE; THRESHOLD VOLTAGE;

VOLTAGE REFERENCES;

CMOS INTEGRATED CIRCUITS;

EID: 0036454666     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. S. Adriaensen, V. Dessard, D. Flandre, "A bandgap circuit operating up to 300°C using lateral bipolar transistors in thin-film CMOS-SOI technology", Proceedings of the IEEE 1999 International SOI Conference (Rohnert Park, CA - USA), October 1999.
2. J.-P. Eggermont, V. Dessard, A. Vandooren, D. Flandre, J.-P. Colinge, "SOI current and voltage reference sources for applications up to 300°C", Fourth International High Temperature Conference (Albuquerque, USA), pp. 55-59, June 1998.
3. Silvaco, Atlas v.5.2.0.R., 1998.
4. D. Flandre et al., " Fully-depleted SOI CMOS technology for low-voltage low-power mixed digital/analog/microwave circuits", Analog Integrated Circuits and Signal Processing, 21 (1999), pp. 213-228.
5. Patent Application PCT/EP01/15023.