Node criticality computation for circuit timing analysis and optimization under NBTI effect

Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Volumn , Issue , 2008, Pages 763-768

  Wang, Wenping ^a   Yang, Shengqi ^b   Cao, Yu ^a  

^a AZ 85281   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICALITY (NUCLEAR FISSION); DEGRADATION; DELAY CIRCUITS; ELECTRIC CURRENTS; ELECTRIC NETWORK ANALYSIS; ELECTRONICS ENGINEERING; NEGATIVE TEMPERATURE COEFFICIENT; NETWORKS (CIRCUITS); OPTIMIZATION; SULFATE MINERALS; THERMODYNAMIC STABILITY; TIME MEASUREMENT;

65NM TECHNOLOGY; CIRCUIT DELAYS; CIRCUIT LIFETIME; CIRCUIT TIMING; COMPUTATION ALGORITHMS; CRITICAL NODES; DESIGN LEVELS; ELECTRONIC DESIGNS; INTERNATIONAL SYMPOSIUM; LIMITING FACTORS; NEGATIVE BIAS- TEMPERATURE-INSTABILITY; OPTIMIZATION FRAMEWORK; TIMING ANALYSIS;

TIMING CIRCUITS;

EID: 49749135199     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2008.4479834     Document Type: Conference Paper

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