An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 511-514

  Wang, Wenping ^a   Reddy, Vijay ^b   Krishnan, Anand T ^b   Vattikonda, Rakesh ^a   Krishnan, Srikanth ^b   Cao, Yu ^a  

^a Arizona State University   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; CMOS INTEGRATED CIRCUITS; FIELD EFFECT TRANSISTORS; OSCILLATORS (ELECTRONIC);

65NM CMOS TECHNOLOGY; CHANNEL HOT CARRIERS; CIRCUIT RELIABILITY; NEGATIVE BIAS TEMPERATURE INSTABILITY; PERFORMANCE DEGRADATION; REACTION-DIFFUSION MODELS; SUBTHRESHOLD AND STRONG INVERSION REGIONS; TRANSISTOR PARAMETERS;

INTEGRATED CIRCUITS;

EID: 84938602082     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405783     Document Type: Conference Paper

References (13)

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