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Volumn , Issue , 2008, Pages 1083-1086

Temperature-aware voltage selection for energy optimization

Author keywords

[No Author keywords available]

Indexed keywords

INDUSTRIAL ENGINEERING; OPTIMIZATION;

EID: 49749098472     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484920     Document Type: Conference Paper
Times cited : (20)

References (13)
  • 2
    • 49749098009 scopus 로고    scopus 로고
    • http://ffmpeg.mplayerhq.hu/
  • 5
    • 22544456242 scopus 로고    scopus 로고
    • Temperature and supply voltage aware performance and power modeling at micro-architecture level
    • July
    • W. P. Liao, L. He, and K. M. Lepak, "Temperature and supply voltage aware performance and power modeling at micro-architecture level," IEEE TonCAD, V24, no. 7, pp. 1042-1053, July 2005.
    • (2005) IEEE TonCAD , vol.24 , Issue.7 , pp. 1042-1053
    • Liao, W.P.1    He, L.2    Lepak, K.M.3
  • 8
    • 0036917242 scopus 로고    scopus 로고
    • Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Lower Power Microprocessors under Dynamic Workloads
    • S. Martin, K. Flautner, T. Mudge, D. Blaauw, Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Lower Power Microprocessors under Dynamic Workloads, ICCAD, pp. 721-725, 2002.
    • (2002) ICCAD , pp. 721-725
    • Martin, S.1    Flautner, K.2    Mudge, T.3    Blaauw, D.4
  • 10
    • 27444438269 scopus 로고    scopus 로고
    • K. Sankaranarayanan, S. Velusamy, M.R. Stan, K. Skadron, A Case for Thermal-Aware Floorplanning at the Microarchitectural Level, The Journal of Instruction-Level Parallelism, V7, Oct. 2005, pp. 1-16.
    • K. Sankaranarayanan, S. Velusamy, M.R. Stan, K. Skadron, A Case for Thermal-Aware Floorplanning at the Microarchitectural Level, The Journal of Instruction-Level Parallelism, V7, Oct. 2005, pp. 1-16.
  • 12
    • 33846578163 scopus 로고    scopus 로고
    • Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip Design
    • Yuan Xie, Wei-Lun Hung, Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip Design, Journal of VLSI Signal Processing, 45(3), pp. 177-189, 2006.
    • (2006) Journal of VLSI Signal Processing , vol.45 , Issue.3 , pp. 177-189
    • Xie, Y.1    Hung, W.-L.2
  • 13
    • 33846192734 scopus 로고    scopus 로고
    • Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis
    • ISAC
    • Y. Yang, Z. Gu, C. Zhu, R. Dick, L. Shang, ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis, IEEE TonCAD, 26(1), pp. 86-99, 2007.
    • (2007) IEEE TonCAD , vol.26 , Issue.1 , pp. 86-99
    • Yang, Y.1    Gu, Z.2    Zhu, C.3    Dick, R.4    Shang, L.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.