-
1
-
-
34548132532
-
-
International Technology Roadmap for Semiconductors
-
"International Technology Roadmap for Semiconductors," 2005, http:// public.itrs.net.
-
(2005)
-
-
-
2
-
-
34548129706
-
Thermal design power
-
"Thermal design power," http://www.cpuheat.wz.cz/html/ IntelPowerConsumption.htm.
-
-
-
-
5
-
-
1542269347
-
Reducing power density through activity migration
-
Aug
-
S. Heo, K. Barr, and K. Asanovic, "Reducing power density through activity migration," in Proc. Int. Symp. Low Power Electronics & Design, Aug. 2003, pp. 217-222.
-
(2003)
Proc. Int. Symp. Low Power Electronics & Design
, pp. 217-222
-
-
Heo, S.1
Barr, K.2
Asanovic, K.3
-
6
-
-
27544457181
-
Exploiting structural duplication for life-time reliability enhancement
-
June
-
J. Srinivasan, et al, "Exploiting structural duplication for life-time reliability enhancement," in Proc. Int. Symp. Computer Architecture, June 2005, pp. 520-531.
-
(2005)
Proc. Int. Symp. Computer Architecture
, pp. 520-531
-
-
Srinivasan, J.1
-
7
-
-
0036917242
-
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
-
Nov
-
S. M. Martin, et al., "Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads," in Proc. Int. Conf. Computer-Aided Design, Nov. 2002, pp. 721-725.
-
(2002)
Proc. Int. Conf. Computer-Aided Design
, pp. 721-725
-
-
Martin, S.M.1
-
8
-
-
4444368993
-
Leakage aware dynamic voltage scaling for real-time embedded systems
-
June
-
R. Jejurikar, C. Pereira, and R. Gupta, "Leakage aware dynamic voltage scaling for real-time embedded systems," in Proc. Design Automation Conf., June 2004, pp. 275-280.
-
(2004)
Proc. Design Automation Conf
, pp. 275-280
-
-
Jejurikar, R.1
Pereira, C.2
Gupta, R.3
-
9
-
-
15744378341
-
Overhead-conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems
-
Jan
-
A. Andrei, et al, "Overhead-conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems," in IEE Proceedings, Jan. 2005, pp. 28-38.
-
(2005)
IEE Proceedings
, pp. 28-38
-
-
Andrei, A.1
-
10
-
-
22544456242
-
Temperature and supply voltage aware performance and power modeling at microarchitecture level
-
July
-
W. P. Liao, L. He, and K. M. Lepak, "Temperature and supply voltage aware performance and power modeling at microarchitecture level," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 7, pp. 1042-1053, July 2005.
-
(2005)
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems
, vol.24
, Issue.7
, pp. 1042-1053
-
-
Liao, W.P.1
He, L.2
Lepak, K.M.3
-
11
-
-
34249306904
-
-
Univ. of Virginia, Tech. Rep, May 2003, CS-2003-05
-
Y. Zhang, et al, "HotLeakage: A temperature-aware model of subthreshold and gate leakage for architects," Univ. of Virginia, Tech. Rep., May 2003, CS-2003-05.
-
HotLeakage: A temperature-aware model of subthreshold and gate leakage for architects
-
-
Zhang, Y.1
-
12
-
-
33646909655
-
Thermal-aware task allocation and scheduling for embedded systems
-
mar
-
W.-L. Hung, et al., "Thermal-aware task allocation and scheduling for embedded systems," in Proc. Design, Automation & Test in Europe Conf., mar. 2005.
-
(2005)
Proc. Design, Automation & Test in Europe Conf
-
-
Hung, W.-L.1
-
13
-
-
34047137947
-
Exploring "temperature-aware design" in low-power mpsocs
-
Mar
-
G. Paci, et al, "Exploring "temperature-aware design" in low-power mpsocs," in Proc. Design, Automation & Test in Europe Conf., Mar. 2006.
-
(2006)
Proc. Design, Automation & Test in Europe Conf
-
-
Paci, G.1
-
16
-
-
0034453479
-
BSIM4 gate leakage model including source-drain partition
-
Dec
-
K. M. Cao, et al., "BSIM4 gate leakage model including source-drain partition," in IEDM Technology Dig., Dec. 2000, pp. 815-818.
-
(2000)
IEDM Technology Dig
, pp. 815-818
-
-
Cao, K.M.1
-
17
-
-
34548129707
-
ISCAS85 benchmarks suite
-
"ISCAS85 benchmarks suite," http://www.visc.vt.edu/mhsiao/ iscas85. html.
-
-
-
-
18
-
-
34548140244
-
System-level leakage power modeling methodology
-
Dept. of Electronics Engg, Tsinghua University, Bachelor's Degree Thesis, July
-
F. Zhang, "System-level leakage power modeling methodology," Dept. of Electronics Engg., Tsinghua University," Bachelor's Degree Thesis, July 2006.
-
(2006)
-
-
Zhang, F.1
-
20
-
-
34047131259
-
Adaptive chip-package thermal analysis for synthesis and design
-
Mar
-
Y. Yang, et al., "Adaptive chip-package thermal analysis for synthesis and design," in Proc. Design, Automation, and Test in Europe, Mar. 2006, pp. 844-849.
-
(2006)
Proc. Design, Automation, and Test in Europe
, pp. 844-849
-
-
Yang, Y.1
-
21
-
-
39749186497
-
Combining genetic algorithms based task mapping and optimal voltage selection for energy efficient distributed system synthesis
-
June
-
Y P. Liu, et al., "Combining genetic algorithms based task mapping and optimal voltage selection for energy efficient distributed system synthesis," in Proc. Int. Conf. Communications, Circuits and Systems, June 2006, pp. 2074-2078.
-
(2006)
Proc. Int. Conf. Communications, Circuits and Systems
, pp. 2074-2078
-
-
Liu, Y.P.1
-
22
-
-
0031681657
-
TGFF: Task graphs for free
-
Mar
-
R. P. Dick, D. L. Rhodes, and W. Wolf, "TGFF: Task graphs for free," in Proc. Int. Wkshp. Hardware/Software Co-Design, Mar. 1998, pp. 97-101.
-
(1998)
Proc. Int. Wkshp. Hardware/Software Co-Design
, pp. 97-101
-
-
Dick, R.P.1
Rhodes, D.L.2
Wolf, W.3
-
23
-
-
34548132529
-
Intel®pentium™processor extreme edition 955 on 65 nm process
-
datasheet
-
"Intel®pentium™processor extreme edition 955 on 65 nm process," 2006, datasheet.
-
(2006)
-
-
-
24
-
-
84886736952
-
New generation of predictive technology model for sub-45nm design exploration
-
Mar
-
W. Zhao and Y Cao, "New generation of predictive technology model for sub-45nm design exploration," in Proc. Int. Symp. Quality of Electronic Design, Mar. 2006, pp. 585-590.
-
(2006)
Proc. Int. Symp. Quality of Electronic Design
, pp. 585-590
-
-
Zhao, W.1
Cao, Y.2
|