A reduced complexity algorithm for minimizing N-detect tests

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2007, Pages 492-497

  Kantipudi, Kalyana R ^a   Agrawal, Vishwani D ^a  

^a AUBURN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER PROGRAMMING LANGUAGES; DYNAMIC PROGRAMMING; INTEGER PROGRAMMING; INTEGRATED CIRCUITS; LINEARIZATION; NUMBER THEORY; PARTICLE SIZE ANALYSIS; RECURSIVE FUNCTIONS; TESTING; TREES (MATHEMATICS);

INTEGER LINEAR PROGRAMMINGS; INTEGER VARIABLES; MULTIPLIER CIRCUITS; NP-HARD; RANDOMIZED ROUNDING; RANDOMIZED ROUNDING METHODS; REAL NUMBERS; REDUCED COMPLEXITIES;

EMBEDDED SYSTEMS;

EID: 48349137675     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2007.24     Document Type: Conference Paper

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