A new ATPG algorithm to limit test set size and achieve multiple detections of all faults

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 94-99

  Lee, Sooryong ^a   Cobb, B ^a   Dworak, J ^a   Grimaila, M R ^a   Mercer, M R ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTIVE PARTS; DYNAMIC COMPACTION; FAULT SIMULATION; GREEDY APPROACHES; MULTIPLE DETECTION; POTENTIAL VALUES; RANDOM EXCITATIONS; SYSTEMATIC METHOD;

EXHIBITIONS;

ALGORITHMS;

EID: 84893755275     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998255     Document Type: Conference Paper

References (5)

1. J. Dworak, J. Wicker, S. Lee, M.R. Grimaila, K.M. Butler, B. Stewart, L.C.Wang and M.R. Mercer, "Defect-oriented testing and defective part level prediction for commercial sub-micron ICs", IEEE Design and Test of Computers Jan.-Feb. 2001, pp.31 41
2. M.R. Grimaila, S. Lee, J. Dworak, K.M. Butler, B. Stewart, H. Balachandran, B. Houchins, V. Mathur, J. Park, L.C. Wang and M.R. Mercer, "REDORandom Excitation and Deterministic Observation-First Commercial Experiment", Proc. 1999 VLSI Test Symposium, 1999, pp. 268-274
3. S.B. Akers, C. Joseph and B. Krishnamurthy, "On the role of independent fault sets in the generation of minimal test sets", Proc. 1987 Int. Test. Conf., 1987, pp. 1100-1107
4. H.K. Lee and D.S. Ha, "An efficient, forward fault simulation algorithm based on the parallel pattern single fault propagation", Proc. 1991 Int. Test. Conf., 1991, pp. 946-955
5. S. Kajihara, I. Pomeranz, K. Kinoshita and S.M. Reddy, "Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits", IEEE Tran. on CAD vol. 14 No. 12, Dec. 1995, pp. 1496-1503