Bottleneck removal algorithm for dynamic compaction in sequential circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 10, 1997, Pages 1157-1172

  Chakradhar, Srimat T ^a   Raghunathan, Anand ^a  

^a NEC LABORATORIES AMERICA   (United States)

Author keywords

Automatic test pattern generation; dynamic compaction; test application time; test set size

Indexed keywords

EID: 0001400513     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.662677     Document Type: Article

References (41)

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