ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing

Journal of Real-Time Image Processing

Volumn 3, Issue 3, 2008, Pages 201-216

  Saponara, Sergio ^a   Casula, Michele ^a   Fanucci, Luca ^a  

^a UNIVERSITY OF PISA   (Italy)

Author keywords

Application specific instruction set processor (ASIP); Low power consumption; Motion estimation; Real time image video processing; Reconfigurable architectures; Retinex

Indexed keywords

COMPUTER GRAPHICS; FILTRATION; IMAGE PROCESSING; IMAGING SYSTEMS; MOTION ESTIMATION; OPTICAL DATA PROCESSING; OPTICAL DESIGN; OPTIMIZATION; VIDEO CAMERAS;

(SPM) CLASSES; AND REAL TIME; APPLICATION-SPECIFIC INSTRUCTION-SET PROCESSOR (ASISP); ARCHITECTURAL LEVELS; CASE STUDIES; CONFIGURABILITY; PERFORMANCE REQUIREMENTS; POST FABRICATION; POWER EFFICIENT; PROCESSING ALGORITHMS; RE CONFIGURABLE ARCHITECTURE; RE-CONFIGURABLE; REAL-TIME IMAGE PROCESSING; RECONFIGURABLE DESIGNS; RECONFIGURABLE HARDWARE (RH); RETINEX; SILICON IMPLEMENTATION; SPECIAL PROCESSOR; SPRINGER (CO);

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 47849113940     PISSN: 18618200     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11554-008-0084-y     Document Type: Article

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