ASIP design for partially structured LDPC codes

Electronics Letters

Volumn 42, Issue 18, 2006, Pages 1048-1049

  Dinoi, L ^b   Martini, R ^a   Masera, G ^a   Quaglio, F ^a   Vacca, F ^a  

^a POLITECNICO DI TORINO   (Italy)

^b ISTITUTO SUPERIORE MARIO BOELLA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); ERROR CORRECTION; LOGIC DESIGN; RANDOM PROCESSES;

APPLICATION SPECIFIC INSTRUCTION SET PROCESSOR (ASIP); LDPC CODES; PARITY CHECK MATRIX;

PROGRAM PROCESSORS;

EID: 33748093602     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20061668     Document Type: Article

References (7)

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2. Kim, E., and Choi, G.S.: ' Diagonal low-density parity-check code for simplified routing in decoder ', IEEE Workshop on Signal Processing, Athens, Greece, November, 2005
3. Ping, L., Leung, W.K., and Phamdo, N.: ' Low density parity check codes with semi-random parity check matrix ', Electron. Lett., 1999, 35, (1), p. 38-39 10.1049/el:19990065 0013-5194
4. Yang, M., Ryan, W.E., and Li, Y.: ' Design of efficiently encodable moderate-length high-rate irregular LDPC codes ', IEEE Trans. Commun., 2004, 52, (4), p. 564-571 10.1109/TCOMM.2004.826367 0090-6778
5. Zhang, Y., Ryan, W.E., and Li, Y.: ' Structured eIRA codes with low floors ', Proc. IEEE Int. Symp. on Information Theory, Adelaide, Australia, September, 2005, p. 174-178
6. Dinoi, L., Sottile, F., and Benedetto, S.: ' Design of variable-rate irregular LDPC codes with low error floor ', Proc. IEEE Int. Conf. on Communications, Seoul, South Korea, May, 2005, 1, p. 647-651
7. Hoffmann, A.: et al. ' A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language ', IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2001, 20, (11), p. 1338-1354 10.1109/43.959863 0278-0070