Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite

2006 International Symposium on System-on-Chip, SOC

Volumn , Issue , 2006, Pages

  Goossens, Gert ^a   Lanneer, Dirk ^a   Geurts, Werner ^a   Van Praet, Johan ^a  

^a Target Compiler Technologies   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CHLORINE COMPOUNDS; COMPLEXATION; ENERGY POLICY; GENERAL PURPOSE COMPUTERS; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; VERIFICATION; VERY LONG INSTRUCTION WORD ARCHITECTURE;

APPLICATION SPECIFIC INSTRUCTION-SET PROCESSORS; ARCHITECTURAL EXPLORATION; COMPLEX SYSTEMS; CONFIGURABLE; DESIGN TIME; ENERGY CONSUMPTION; GENERAL-PURPOSE PROCESSOR; HARDWARE ACCELERATORS; HARDWARE SYNTHESIS; INTERNATIONAL SYMPOSIUM; MULTI CORES; MULTI PROCESSORS; OPTIMAL BALANCE; RETARGETABLE; SOFTWARE COMPILATION; SYSTEM ON CHIPS; TOOL SUITES; VECTOR PROCESSORS;

PROGRAM COMPILERS;

EID: 50049107175     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSOC.2006.321968     Document Type: Conference Paper

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