-
2
-
-
33750537949
-
Dense structurefrom-motion: An approach based on segment matching
-
Copenhagen, Paper no. LCNS 2531
-
F. Ernst, P. Wilinski, and K. van Overveld, "Dense structurefrom-motion: an approach based on segment matching," in Proc. ECCV, Copenhagen, 2002, Paper no. LCNS 2531, pp. II:17-II:23.
-
(2002)
Proc. ECCV
-
-
Ernst, F.1
Wilinski, P.2
Van Overveld, K.3
-
4
-
-
84908570393
-
A core for ambient and mobile intelligent imaging applications
-
J. Jachalsky, M. Wahle, P. Pirsch, S. Capperon. W. Gehrke, W. M. Kruijtzer, and A. Nuñez, "A core for ambient and mobile intelligent imaging applications," in Proc. IEEE Int. Conf. Multimedia and Expo (ICME), 2003, pp. II-1-4.
-
(2003)
Proc. IEEE Int. Conf. Multimedia and Expo (ICME)
-
-
Jachalsky, J.1
Wahle, M.2
Pirsch, P.3
Capperon, S.4
Gehrke, W.5
Kruijtzer, W.M.6
Nuñez, A.7
-
5
-
-
0033644967
-
Video format conversion
-
G. de Haan, "Video format conversion," J. Society Inform. Display (SID), vol. 8, no. 1, pp. 79-87, 2000.
-
(2000)
J. Society Inform. Display (SID)
, vol.8
, Issue.1
, pp. 79-87
-
-
De Haan, G.1
-
6
-
-
0003715195
-
-
Norwell, MA: Kluwer
-
V. Bhaskaran and K. Konstantinides, Image and Video Compression Standards, Algorithms and Architectures, 2nd ed. Norwell, MA: Kluwer, 1997.
-
(1997)
Image and Video Compression Standards, Algorithms and Architectures, 2nd Ed.
-
-
Bhaskaran, V.1
Konstantinides, K.2
-
7
-
-
27644550513
-
-
Adelante Technologies. [Online]
-
A|RT Designer and A|RT Builder Tools. Adelante Technologies. [Online], Available: http://www.adelantetechnologies.com
-
A|RT Designer and A|RT Builder Tools
-
-
-
8
-
-
84983094542
-
A design methodology for high performance les: Wireless broadband radio basedband case study
-
Sep.
-
V. Aue, J. Kneip, M. Weiss, M. Bolle, and G. Fetweis, "A design methodology for high performance les: wireless broadband radio basedband case study," in Proc. EuroMicro Symp. Digital System Design, Sep. 2001, pp. 16-20.
-
(2001)
Proc. EuroMicro Symp. Digital System Design
, pp. 16-20
-
-
Aue, V.1
Kneip, J.2
Weiss, M.3
Bolle, M.4
Fetweis, G.5
-
9
-
-
85008025144
-
A novel methodology for the design of application-specific instruction-set processors (ASIP) using a machine description language
-
Nov.
-
A. Hoffmann, A. Nohl, G. Braun, O. Schliebusch, T. Kogel, and H. Meyr, "A novel methodology for the design of application-specific instruction-set processors (ASIP) using a machine description language," IEEE Trans. Comput. Aided Design Integr. Circuits Syst., vol. 20, no. 11, pp. 1338-1354, Nov. 2001.
-
(2001)
IEEE Trans. Comput. Aided Design Integr. Circuits Syst.
, vol.20
, Issue.11
, pp. 1338-1354
-
-
Hoffmann, A.1
Nohl, A.2
Braun, G.3
Schliebusch, O.4
Kogel, T.5
Meyr, H.6
-
10
-
-
0002421081
-
CHESS: Retargetable code generation for embedded DSP processors
-
P. Marwedel, Ed. Norwell, MA: Kluwer
-
D. Lanneer, J. van Praet, A. Kifli, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens, "CHESS: retargetable code generation for embedded DSP processors," in Code Generation for Embedded Processors, P. Marwedel, Ed. Norwell, MA: Kluwer, 1995.
-
(1995)
Code Generation for Embedded Processors
-
-
Lanneer, D.1
Van Praet, J.2
Kifli, A.3
Schoofs, K.4
Geurts, W.5
Thoen, F.6
Goossens, G.7
-
11
-
-
0035311949
-
Embedded computer architecture and automation
-
Apr.
-
B. Ramakrishna Rau and M. S. Schlansker, "Embedded computer architecture and automation," IEEE Computer, vol. 34, pp. 75-81, Apr. 2001.
-
(2001)
IEEE Computer
, vol.34
, pp. 75-81
-
-
Rau, B.R.1
Schlansker, M.S.2
-
12
-
-
0036792825
-
C-HEAP: A heterogeneous multiprocessor architecture template and scalable and flexible protocol for the design of embedded signal processing systems
-
A. Nieuwland, J. Kang, O. P. Gangwal, R. Sethuraman, N. Busa', R. P. Llopis, K. Goosens, and P. Lippens, "C-HEAP: a heterogeneous multiprocessor architecture template and scalable and flexible protocol for the design of embedded signal processing systems," Design Automation Embedded Syst., vol. 3, pp. 233-270, 2002.
-
(2002)
Design Automation Embedded Syst.
, vol.3
, pp. 233-270
-
-
Nieuwland, A.1
Kang, J.2
Gangwal, O.P.3
Sethuraman, R.4
Busa, N.5
Llopis, R.P.6
Goosens, K.7
Lippens, P.8
-
13
-
-
0027683149
-
True motion estimation with 3-D recursive search block-matching
-
Oct.
-
G. de Haan, P. Biezen, H. Huijgen, and A. Ojo, "True motion estimation with 3-D recursive search block-matching," IEEE Trans. Circuits Syst. Video Technol., vol. 3, no. 10, pp. 368-379, Oct. 1993.
-
(1993)
IEEE Trans. Circuits Syst. Video Technol.
, vol.3
, Issue.10
, pp. 368-379
-
-
De Haan, G.1
Biezen, P.2
Huijgen, H.3
Ojo, A.4
-
14
-
-
0036475447
-
A tutorial on particle filter for on-line nonlinear/non-Gaussian Bayesian tracking
-
Feb.
-
S. Arulampalam, S. Maskell, N. Gordon, and T. Clapp, "A tutorial on particle filter for on-line nonlinear/non-Gaussian Bayesian tracking," IEEE Trans.Signal Process., vol. 50, no. 2, pp. 174-188, Feb. 2002.
-
(2002)
IEEE Trans.Signal Process.
, vol.50
, Issue.2
, pp. 174-188
-
-
Arulampalam, S.1
Maskell, S.2
Gordon, N.3
Clapp, T.4
-
15
-
-
0035435880
-
Real-time recursive motion segmentation of video data on a programmable device
-
Aug.
-
R. Wittebrood and G. de Haan, "Real-time recursive motion segmentation of video data on a programmable device," IEEE Trans. Consumer Electron., vol. 47, pp. 559-567, Aug. 2001.
-
(2001)
IEEE Trans. Consumer Electron.
, vol.47
, pp. 559-567
-
-
Wittebrood, R.1
De Haan, G.2
-
16
-
-
2342495689
-
A technique for reducing complexity of recursive motion estimation algorithms
-
Aug.
-
A. Berić, G. de Haan, R. Sethuraman, and J. van Meerbergen, "A technique for reducing complexity of recursive motion estimation algorithms," in Proc. IEEE Workshop Signal Processing Syst., Aug. 2003, pp. 195-200.
-
(2003)
Proc. IEEE Workshop Signal Processing Syst.
, pp. 195-200
-
-
Berić, A.1
De Haan, G.2
Sethuraman, R.3
Van Meerbergen, J.4
-
17
-
-
0344272198
-
Toward an efficient high quality picturerate up-converter
-
Sep.
-
A. Berić, G. de Haan, J. van Meerbergen, and R. Sethuraman, "Toward an efficient high quality picturerate up-converter," in Proc. IEEE Int. Conf. Image Processing, Sep. 2003, pp. 363-366.
-
(2003)
Proc. IEEE Int. Conf. Image Processing
, pp. 363-366
-
-
Berić, A.1
De Haan, G.2
Van Meerbergen, J.3
Sethuraman, R.4
-
18
-
-
0000087207
-
The semantics of a simple language for parallel programming
-
J. Rosenfeld, Ed. Amsterdam, The Netherlands: North-Holland Publishing Co.
-
G. Kahn, "The semantics of a simple language for parallel programming," in Information Processing, J. Rosenfeld, Ed. Amsterdam, The Netherlands: North-Holland Publishing Co., 1974.
-
(1974)
Information Processing
-
-
Kahn, G.1
-
19
-
-
0010764837
-
RAPIDO: A modular, multiboard, heterogeneous multiprocessor, PCI-bus based prototyping framework for the validation of SoC VLSI designs
-
N. Busa', G. Alkadi, M. Verberne, R. Peset LLopis, and S. Ramanathan, "RAPIDO: a modular, multiboard, heterogeneous multiprocessor, PCI-bus based prototyping framework for the validation of SoC VLSI designs," in Proc. IEEE Workshop Rapid System Prototyping, 2002, pp. 159-165.
-
(2002)
Proc. IEEE Workshop Rapid System Prototyping
, pp. 159-165
-
-
Busa, N.1
Alkadi, G.2
Verberne, M.3
Llopis, R.P.4
Ramanathan, S.5
-
20
-
-
33646432074
-
Improving the efficiency of memory partitioning by address clustering
-
A. Macii, E. Macii, and M. Poncino, "Improving the efficiency of memory partitioning by address clustering," in Design Automation Test in Europe Conf. Exhibition, 2003, pp. 18-23.
-
(2003)
Design Automation Test in Europe Conf. Exhibition
, pp. 18-23
-
-
Macii, A.1
Macii, E.2
Poncino, M.3
-
21
-
-
0036543065
-
Layout-driven memory synthesis for embedded systems-on-chip
-
Apr.
-
L. Benini, L. Macchiarulo, A. Macci, and M. Poncino, "Layout-driven memory synthesis for embedded systems-on-chip," IEEE Trans. Very Large Scale Integr. Syst., vol. 10, no. 2, pp. 96-105, Apr. 2002.
-
(2002)
IEEE Trans. Very Large Scale Integr. Syst.
, vol.10
, Issue.2
, pp. 96-105
-
-
Benini, L.1
Macchiarulo, L.2
Macci, A.3
Poncino, M.4
-
22
-
-
2342481696
-
2. motion estimator for picturerate up-converter
-
Jan.
-
2. motion estimator for picturerate up-converter," in Proc. 17th IEEE Int. Conf. VLSI Design, Jan. 2004, pp. 1083-1088.
-
(2004)
Proc. 17th IEEE Int. Conf. VLSI Design
, pp. 1083-1088
-
-
Berić, A.1
Sethuraman, R.2
Peters, H.3
Van Meerbergen, J.4
De Haan, G.5
Pinto, C.A.6
|