Alternatives in designing level-restoring buffers for interconnection networks in field-programmable gate arrays

Proceedings - 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007

Volumn , Issue , 2007, Pages 138-146

  Miller, Scott ^a   Sima, Mihai ^a   McGuire, Michael ^a  

^a UNIVERSITY OF VICTORIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; ELECTRIC POWER UTILIZATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC GATES; MICROPROCESSOR CHIPS; SYSTEMS ANALYSIS; TRANSISTORS;

90 NM TECHNOLOGIES; ACTIVE FEEDBACKS; ACTIVE POWERS; AREA PENALTIES; CIRCUIT TECHNIQUES; ENERGY PRODUCTS; IN FIELDS; LOGIC VALUES; NOISE MARGINS; PASS TRANSISTORS; PROPAGATION DELAYS; STATIC POWER CONSUMPTIONS; SWITCHING TIMES; TRANSITION EDGES;

ARCHITECTURAL DESIGN;

EID: 47749135246     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2007.4341461     Document Type: Conference Paper

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