Compact modeling of suspended gate FET

Proceedings of the IEEE International Frequency Control Symposium and Exposition

Volumn , Issue , 2008, Pages 119-124

  Chauhan, Y S ^a   Tsamados, D ^a   Abele N ^a,b   Eggimann, C ^c   Declercq, M ^a   Ionescu, A M ^a  

^a EPFL   (Switzerland)

^b STMICROELECTRONICS   (France)

^c Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FIELD EFFECT TRANSISTORS; MESFET DEVICES; POWDERS;

AND GATES; COMPACT MODELING; EXCELLENT PERFORMANCE; INTERNATIONAL CONFERENCES; MULTI-PHYSICS; NUMERICAL DEVICE SIMULATION; NUMERICAL SIMULATIONS; PULL-IN; PULL-OUT; SPECTRE SIMULATORS; SUSPENDED GATE (SG); SUSPENDED GATE FET (SGFET); VERILOG-A; VLSI DESIGNS;

CIRCUIT SIMULATION;

EID: 47649132953     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.2008.11     Document Type: Conference Paper

References (13)

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