Numerical and analytical simulations of Suspended Gate - FET for ultra-low power inverters

ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference

Volumn 2007, Issue , 2007, Pages 167-170

  Tsamados, D ^a   Chauhan, Y S ^a   Eggimann, C ^a   Akarvardar, K ^b   Philip Wong, H S ^b   Ionescu, Adrian M ^a  

^a EPFL   (Switzerland)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC INVERTERS; GATE DIELECTRICS; MEMS; SOLID STATE DEVICES;

LEAKAGE POWER; ULTRA LOW POWER INVERTERS;

FIELD EFFECT TRANSISTORS;

EID: 39549114801     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2007.4430905     Document Type: Conference Paper

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