High-performance designs for linear algebra operations on reconfigurable hardware

IEEE Transactions on Computers

Volumn 57, Issue 8, 2008, Pages 1057-1071

  Zhuo, Ling ^a   Prasanna, Viktor K ^a  

^a University of Southern California   (United States)

Author keywords

Computations on matrices; Parallel algorithms; Reconfigurable hardware

Indexed keywords

ALGEBRA; BOOLEAN ALGEBRA; DIGITAL ARITHMETIC; EIGENVALUES AND EIGENFUNCTIONS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GENERAL PURPOSE COMPUTERS; MATRIX ALGEBRA;

CHIP AREAS; FIELD PROGRAMMABLE GATE ARRAY (FPGA); FLOATING-POINT UNIT (FPU); GENERAL PURPOSE PROCESSOR (GPP); HARDWARE ACCELERATIONS; HARDWARE CONSTRAINTS; HARDWARE RESOURCES; HIGH-PERFORMANCE DESIGNS; I/O PINS; LINEAR ALGEBRA OPERATIONS; MATRIX FACTORIZATIONS; MATRIX MULTIPLICATIONS; MATRIX VECTOR MULTIPLICATION (MVM); MEMORY BANDWIDTHS; NUMERICAL LINEAR ALGEBRA; PERFORMANCE OPTIMIZATIONS; RECONFIGURABLE HARDWARE (RH); XILINX VIRTEX;

LINEAR ALGEBRA;

EID: 47049109081     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2008.55     Document Type: Article

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