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Volumn , Issue , 2006, Pages 249-258

Advanced components in the variable precision floating-point library

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PARALLEL PROCESSING SYSTEMS; PRECISION ENGINEERING; PROGRAM PROCESSORS; SET THEORY;

EID: 34547396571     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2006.21     Document Type: Conference Paper
Times cited : (39)

References (17)
  • 2
    • 0028501884 scopus 로고
    • Field programmable gate arrays and floating point arithmetic
    • Sept
    • B. Fagin and C. Renard, "Field programmable gate arrays and floating point arithmetic," IEEE Transactions on VLSI Systems, vol. 2, pp. 365-367, Sept. 1994.
    • (1994) IEEE Transactions on VLSI Systems , vol.2 , pp. 365-367
    • Fagin, B.1    Renard, C.2
  • 3
    • 0029507865 scopus 로고
    • Quantitative analysis of floating point arithmetic on FPGA based custom computing machines
    • April
    • N. Shirazi, A. Walters, and P. Athanas, "Quantitative analysis of floating point arithmetic on FPGA based custom computing machines," in IEEE Symposium on FPGAs for Custom Computing Machines, pp. 155-162, April 1995.
    • (1995) IEEE Symposium on FPGAs for Custom Computing Machines , pp. 155-162
    • Shirazi, N.1    Walters, A.2    Athanas, P.3
  • 4
    • 0030396384 scopus 로고    scopus 로고
    • Implementation of IEEE single precision floating point addition and multiplication on FPGAs
    • April
    • L. Louca, T. A. Cook, and W. H. Johnson, "Implementation of IEEE single precision floating point addition and multiplication on FPGAs," in IEEE Symposium on FPGAs for Custom Computing Machines, pp. 107-116, April 1996.
    • (1996) IEEE Symposium on FPGAs for Custom Computing Machines , pp. 107-116
    • Louca, L.1    Cook, T.A.2    Johnson, W.H.3
  • 6
    • 0036385677 scopus 로고    scopus 로고
    • A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs
    • Feb
    • J. Dido, N. Geraudie, et al., "A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs," in International Symposium on Field Programmable Gate Arrays, pp. 50-55, Feb. 2002.
    • (2002) International Symposium on Field Programmable Gate Arrays , pp. 50-55
    • Dido, J.1    Geraudie, N.2
  • 12
    • 0033733825 scopus 로고    scopus 로고
    • Accelerating pipelined integer and floating-point accumulations in configurable hardware with delayed addition techniques
    • March
    • Z. Luo and M. Martonosi, "Accelerating pipelined integer and floating-point accumulations in configurable hardware with delayed addition techniques," in IEEE Transactions on Computers, vol. 49, pp. 208-218, March 2000.
    • (2000) IEEE Transactions on Computers , vol.49 , pp. 208-218
    • Luo, Z.1    Martonosi, M.2
  • 13
    • 34547424384 scopus 로고    scopus 로고
    • A VHDL library of parametrisable floating-point and LNS operators for FPGA
    • "A VHDL library of parametrisable floating-point and LNS operators for FPGA." http://perso.ens-lyon.fr/jeremie.detrey/FPLibrary/.
  • 16
    • 0034215449 scopus 로고    scopus 로고
    • Reciprocation, square root, inverse square root, and some elementary functions using small multipliers
    • July
    • M. D. Ercegovac, T. Lang, J.-M. Muller, and A. Tisserand, "Reciprocation, square root, inverse square root, and some elementary functions using small multipliers," IEEE Transactions on Computers, vol. 49, pp. 628-637, July 2000.
    • (2000) IEEE Transactions on Computers , vol.49 , pp. 628-637
    • Ercegovac, M.D.1    Lang, T.2    Muller, J.-M.3    Tisserand, A.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.