Optimizing FPGA-based vector product designs

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn , Issue , 1999, Pages 188-197

  Benyamin, Daniel ^a   Luk, Wayne ^b   Villasenor, John ^a  

^a University of California   (United States)

^b IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CONSTRAINT THEORY; DATA STRUCTURES; DIGITAL ARITHMETIC; DISTRIBUTED COMPUTER SYSTEMS; FIR FILTERS; OPTIMIZATION; RESPONSE TIME (COMPUTER SYSTEMS); VECTORS;

DATA PATTERNS; DISTRIBUTED ARITHMETIC; MULTIPLE CONSTANT MULTIPLIER TREES; RESOURCE UTILIZATION; VECTOR PRODUCT DESIGNS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0033488513     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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