Design feasibility study for a 500 Gbits/s AES cypher decypher engine

Proceedings of the International Conference on Microelectronics, ICM

Volumn , Issue , 2006, Pages 190-193

  Bouhraoua, A ^a  

^a KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS   (Saudi Arabia)

Author keywords

AES; ASICs; High speed architectures; High throughput

Indexed keywords

CRYPTOGRAPHY; DECISION MAKING; ELECTRONICS INDUSTRY; MICROELECTRONICS; PLANNING;

(E ,3E) PROCESS; AES ENCRYPTION; DESIGN FEASIBILITY; FEASIBILITY STUDIES; INTERNATIONAL CONFERENCES; REGULAR SOLUTION;

RESOURCE ALLOCATION;

EID: 46749155881     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICM.2006.373299     Document Type: Conference Paper

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