A 10 Gbps full-AES crypto design with a twisted-BDD S-box architecture

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2002, Pages 98-103

  Morioka, Sumio ^a   Satoh, Akashi ^a  

^a IBM JAPAN LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; CRYPTOGRAPHY; FUNCTIONS; LOGIC CIRCUITS; MATHEMATICAL TRANSFORMATIONS; POLYNOMIALS; TABLE LOOKUP;

ADVANCED ENCRYPTION STANDARD; AFFINE TRANSFORMATION; CIPHER BLOCK CHAINING MODE; PROPAGATION DELAY; T-BOX ALGORITHM; TWISTED-BINARY DECISION DIAGRAM;

LOGIC DESIGN;

EID: 0036398166     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

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