Minimum area cost for a 30 to 70 Gbits/s AES processor

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Volumn , Issue , 2004, Pages 83-88

  Hodjat, Alireza ^a   Verbauwhede, Ingrid ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COUNTER MODE; DESIGN DECISIONS; KEY SCHEDULING; PIPELINING;

COMPUTABILITY AND DECIDABILITY; CRYPTOGRAPHY; OPTICAL LINKS; OPTIMIZATION; SECURITY OF DATA; STANDARDS;

PROGRAM PROCESSORS;

EID: 4544342362     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2004.1339512     Document Type: Conference Paper

References (12)

1. National Institute of Standards and Technology (U.S.), Advanced Encryption Standard. Available at: http://csrc.nist.gov/publication/drafts/dfips-AES.pdf
2. M. Dworkin, SP 800-38A 2001, "Recommendation for Block Cipher Modes of Operations", December 01.
3. A. Satoh et al, "A Compact Rijndael Hardware Architecture with S-Box Optimization", ASIACRYPT 2001, LNCS 2248, pp. 239-254, 2001.
4. http://www.nist.gov/aes/
5. H. Kuo, P. Schaumont, and I. Verbauwhede, "A 2,29 Gbits.sec, 56 mW non-pipelined Rijndael AES Encryption IC in a 1.8 V, 0.18 um CMOS technology," Proc. 2002 CICC, pp. 147-50, May 2002.
6. J. Wolkerstorfer, E. Oswald, M. Lamberger, "An ASIC Implementation of the AES Sboxes", Proc. RSA Conference 2002, San Jose, CA, February 2002.
7. M. McLoone, J. McCanny, "High Performance Single Chip FPGA Rijndael Algorithm Implementations", Workshop on Cryptographic Hardware and Embedded Systems, Paris, 2001.
8. A. Elbirt, W. Yip, B. Chetwynd, C. Paar, "An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists", IEEE Trans. of VLSI Systems, 9.4, pp.545-557, August 2001.
9. T. Ichikawa et al, "Hardware Evaluation of the AES Finalists", in Proc. 3th AES Candidate Conference, New York, April 13-13, 2000.
10. I. Verbauwhede, P. Schaumont, H. Kuo, "Design and Performance testing of a 2.29 Gb/s Rijndael Processor", IEEE Journal of Solid-State Circuits (JSSC), March 2003.
11. V. Rijmen, "Efficient Implemenation of the Rijndael S-box", available at: http://www.esat.kuleuven.ac.be/~rijmen/rijndael/sbox.pdf
12. th Asilomar Conference on Signals, Systems, and Computers, November 2003.