An efficient 21.56GBPS AES implementation on FPGA

Conference Record - Asilomar Conference on Signals, Systems and Computers

Volumn 1, Issue , 2004, Pages 465-470

  Zhang, Xinmiao ^a   Parhi, Keshab K ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADVANCED ENCRYPTION STANDARD (AES) ALGORITHMS; CELLULAR PHONES; HIGH-SPEED ARCHITECTURES; NON-FEEDBACK MODES;

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; CRYPTOGRAPHY; DATA COMMUNICATION SYSTEMS; MATHEMATICAL TRANSFORMATIONS; POLYNOMIALS; SECURITY OF DATA; SERVERS; SMART CARDS; WORLD WIDE WEB;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 21644486058     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

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