Integrated design of AES (Advanced Encryption Standard) encrypter and decrypter

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn 2002-January, Issue , 2002, Pages 277-285

  Lu, Chih Chung ^a   Tseng, Shau Yin ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

Application software; Communication standards; Computer architecture; Cryptography; Data security; Design optimization; Hardware; Internet; NIST; Smart cards

Indexed keywords

APPLICATION PROGRAMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DATA PRIVACY; DESIGN; HARDWARE; INTERNET; SECURITY OF DATA; SMART CARDS; TRANSPORTATION;

ADVANCED ENCRYPTION STANDARD; COMMUNICATION STANDARDS; CRITICAL APPLICATIONS; DESIGN OPTIMIZATION; ENCRYPTION/DECRYPTION; NIST; PROPOSED ARCHITECTURES; VERY LOW COMPLEXITY;

CRYPTOGRAPHY;

EID: 67649903039     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2002.1030726     Document Type: Conference Paper

References (8)

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3. E. Barker, L. Bassham, W. burr, M. Dworkin, J. Foti, J. Nechvatal, and E. Roback, "Report on the Development of the Advanced Encryption Standard (AES)." Available at http://home.ecn.ab.ca/~jsavard/crypto/co040801.htm.
4. "Advanced Encryption Standard (AES)" Federal Information Processing Standards Publication 197, Nov. 26, 2001.
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8. M. Mcloone, J.V McCanny, "High Performance Single-Chip FPGA Rijndael Algorithm Implementation." Cryptographic Hardware and Embedded Systems, Workshop on Cryptographic Hardware and Embedded Systems, May 14-16, 2001.