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Volumn 2162, Issue , 2001, Pages 51-64
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Architectural optimization for a 1.82gbits/sec VLSI implementation of the AES rijndael algorithm
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER HARDWARE DESCRIPTION LANGUAGES;
DATA PRIVACY;
EMBEDDED SYSTEMS;
INTEGRATED CIRCUIT DESIGN;
MEMORY ARCHITECTURE;
VLSI CIRCUITS;
ADVANCED ENCRYPTION STANDARD;
DATA ENCRYPTION;
DISTRIBUTED MEMORY;
HARDWARE ARCHITECTURE;
HARDWARE DESIGN;
RIJNDAEL ALGORITHM;
STANDARD CELL;
VLSI IMPLEMENTATION;
CRYPTOGRAPHY;
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EID: 35248861095
PISSN: 03029743
EISSN: 16113349
Source Type: Book Series
DOI: 10.1007/3-540-44709-1_6 Document Type: Conference Paper |
Times cited : (101)
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References (7)
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