Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept

ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 304-307

  Tajalli, Armin ^a   Vittoz, Eric ^a   Leblebici, Yusuf ^a   Brauer, Elizabeth J ^b  

^a EPFL   (Switzerland)

^b Northern Arizona University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; FUZZY LOGIC; HEALTH; LOADS (FORCES); LOGIC CIRCUITS; LOGIC DEVICES; MICROFLUIDICS; NETWORKS (CIRCUITS); SODIUM; SWITCHING CIRCUITS; SWITCHING THEORY; TECHNOLOGY;

(P ,P ,T) MEASUREMENTS; CMOS GATES; CMOS TECHNOLOGIES; EUROPEAN; HIGH RESISTANCE; LOW BIAS; MOS CURRENT MODE LOGIC (MCML); POWER DELAYS; SOLID-STATE CIRCUITS CONFERENCE; SUB THRESHOLDS; SUBTHRESHOLD REGIME; ULTRA LOW POWER (ULP); WIDE FREQUENCY RANGE;

BIAS CURRENTS;

EID: 44849114467     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2007.4430304     Document Type: Conference Paper

References (7)

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7. F. Cannillo, and C Toumazou, "Nano-power subthreshold current-mode logic in sub-100nm technologies," IEE Electronics Letters, vol. 41, no. 23, November 2005.