Breaking the power-delay tradeoff: Design of low-power high-speed MOS current-mode logic circuits operating with reduced supply voltage

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 1871-1874

  Badel, Stéphane ^a   Leblebici, Yusuf ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

BIAS CURRENTS; CMOS INTEGRATED CIRCUITS; LOGIC CIRCUITS; VOLTAGE CONTROL;

NEGATIVE BIAS STRATEGY; POWERDELAY PRODUCTS; SUPPLY VOLTAGE;

MOS DEVICES;

EID: 34548851757     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378280     Document Type: Conference Paper

References (7)

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7. J. Musicer, "An analysis of MOS current mode logic for low. power and high performance digital, logic," Master's thesis, UC. Berkeley, 2000.