Nano-power subthreshold current-mode logic in sub-100 nm technologies

Electronics Letters

Volumn 41, Issue 23, 2005, Pages 17-18

  Cannillo, F ^a   Toumazou, C ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC INVERTERS; FORMAL LOGIC; GATES (TRANSISTOR); MOS DEVICES; NANOTECHNOLOGY;

DC PERFORMANCE; INVERTER GATE; MOS CURRENT-MODE LOGIC (MCML); SUB-100 NM TECHNOLOGIES;

DIGITAL CIRCUITS;

EID: 28244448589     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20053082     Document Type: Article

References (7)

1. Borkar, S.: ' Design challenges of technology scaling ', IEEE Micro, 1999, 19, (4), p. 23-29
2. Soeleman, H., Roy, K., and Paul, B.C.: ' Robust subthreshold logic for ultra-low power operation ', IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2001, 9, (1), p. 90-99
3. Martin, M.N.: et al. ' Current-mode differential logic circuits for low power digital systems ', IEEE 39th Midwest Symp. on Circuits and Systems, August 1996, 1, p. 183-186
4. Musicer, J.M., and Rabaey, J.: ' MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments ', Proc. of Int. Symp. on Low Power Electronics and Design, 2000, p. 102-107
5. Troutman, R.R.: ' VLSI limitations from drain-induced barrier lowering ', IEEE Trans. Electron Devices, 1979, 26, (4), p. 461-469
6. Sheu, B.J.: et al. ' BSIM: Berkeley short-channel IGFET model for MOS transistors ', IEEE J. Solid-State Circuits, 1987, 22, (4), p. 558-566
7. Mead, C.: ' Analog VLSI and neural systems ', (Addison Wesley 1989)