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Volumn 1, Issue , 2007, Pages 169-172

SMAP: An intelligent mapping tool for network on chip

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; ELECTRIC NETWORK TOPOLOGY; ENERGY POLICY; INTEGRATED CIRCUITS;

EID: 46449119799     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCS.2007.4292678     Document Type: Conference Paper
Times cited : (23)

References (20)
  • 1
    • 27644494723 scopus 로고    scopus 로고
    • Umit Y Ogras, Jingcao Hu, Radu Marculescu, Key research problems in NoC design: a holistic perspective, CODES+ISSS'05, Sept. 19-21, 2005, Jersey City, New Jersey, USA.
    • Umit Y Ogras, Jingcao Hu, Radu Marculescu, "Key research problems in NoC design: a holistic perspective", CODES+ISSS'05, Sept. 19-21, 2005, Jersey City, New Jersey, USA.
  • 3
    • 24144461667 scopus 로고    scopus 로고
    • Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
    • August
    • Partha Pratim Pande,A. Ivanov and R. Saleh, "Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures" IEEE Transactions on Computers, vol. 54, No. 8, August 2005, pp 1025-1040
    • (2005) IEEE Transactions on Computers , vol.54 , Issue.8 , pp. 1025-1040
    • Pratim Pande, P.1    Ivanov, A.2    Saleh, R.3
  • 4
    • 0034848112 scopus 로고    scopus 로고
    • Route Packets, Not Wires: On-Chip Interconnection Networks
    • June
    • W. J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," in Proc. DAC'01, pp. 684-689, June 2001
    • (2001) Proc. DAC'01 , pp. 684-689
    • Dally, W.J.1    Towles, B.2
  • 5
    • 0006366481 scopus 로고    scopus 로고
    • Network on a Chip: An architecture for billion transistor era
    • November
    • A. Hemanni, "Network on a Chip: An architecture for billion transistor era", Proceedings of the IEEE NorChip Conference, November 2000
    • (2000) Proceedings of the IEEE NorChip Conference
    • Hemanni, A.1
  • 6
    • 84954421164 scopus 로고    scopus 로고
    • Energy-Aware Mapping for Tile-based NoC Architectures Under Performance Constraints
    • Jan
    • J. Hu and R. Marculescu, "Energy-Aware Mapping for Tile-based NoC Architectures Under Performance Constraints," in Proc. ASP-DAC'03, pp. 233-239, Jan 2003.
    • (2003) Proc. ASP-DAC'03 , pp. 233-239
    • Hu, J.1    Marculescu, R.2
  • 7
    • 84944322013 scopus 로고    scopus 로고
    • A Two-step Genetic Algorithm for Mapping Task Graphs to Network on Chip Architecture
    • Sept
    • T. Lei and S. Kumar, "A Two-step Genetic Algorithm for Mapping Task Graphs to Network on Chip Architecture," in Proc. DSD'03, pp. 180-187, Sept. 2003
    • (2003) Proc. DSD'03 , pp. 180-187
    • Lei, T.1    Kumar, S.2
  • 11
    • 84893687806 scopus 로고    scopus 로고
    • A generic architecture for on-chip packet switched interconnections
    • March
    • P.Guerrier, A.Greiner,"A generic architecture for on-chip packet switched interconnections", DATE 2000, pp. 250-256, March 2000.
    • (2000) DATE 2000 , pp. 250-256
    • Guerrier, P.1    Greiner, A.2
  • 12
    • 84893753441 scopus 로고    scopus 로고
    • Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip
    • Mar
    • E.Rijpkema, "Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip",DATE 2003, pp. 350-355, Mar 2003.
    • (2003) DATE 2003 , pp. 350-355
    • Rijpkema, E.1
  • 13
    • 0026174959 scopus 로고
    • OREGAMI: Tools for Mapping Parallel Computations to Parallel Architectures
    • V.Lo et al.,"OREGAMI: Tools for Mapping Parallel Computations to Parallel Architectures",Intl Journal of Parallel Programming, vol. 20, no. 3, 1991, pp. 237-270.
    • (1991) Intl Journal of Parallel Programming , vol.20 , Issue.3 , pp. 237-270
    • Lo, V.1
  • 14
    • 84959877163 scopus 로고    scopus 로고
    • An Efficient Algorithm for the Physical Mapping of Clustered Task Graphs onto Multiprocessor Architectures
    • Jan
    • N.Koziris et al.,"An Efficient Algorithm for the Physical Mapping of Clustered Task Graphs onto Multiprocessor Architectures", Proc. of 8th EuroPDP, pp. 406-413, Jan, 2000.
    • (2000) Proc. of 8th EuroPDP , pp. 406-413
    • Koziris, N.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.